[llvm] e06767f - [AArch64] Regenerate some test checks. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 16 00:30:18 PDT 2021
Author: David Green
Date: 2021-09-16T08:30:08+01:00
New Revision: e06767fdcbe3215773c53166b25e2bf24110119f
URL: https://github.com/llvm/llvm-project/commit/e06767fdcbe3215773c53166b25e2bf24110119f
DIFF: https://github.com/llvm/llvm-project/commit/e06767fdcbe3215773c53166b25e2bf24110119f.diff
LOG: [AArch64] Regenerate some test checks. NFC
This regenerates some of the tests that had very-close-to-updated check
line already, in order to make them more maintainable.
Added:
Modified:
llvm/test/CodeGen/AArch64/fdiv_combine.ll
llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fdiv_combine.ll b/llvm/test/CodeGen/AArch64/fdiv_combine.ll
index 8ebee3c682872..e46986b7e9eed 100644
--- a/llvm/test/CodeGen/AArch64/fdiv_combine.ll
+++ b/llvm/test/CodeGen/AArch64/fdiv_combine.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-neon-syntax=apple -verify-machineinstrs -o - %s | FileCheck %s
; Test signed conversion.
-; CHECK-LABEL: @test1
-; CHECK: scvtf.2s v0, v0, #4
-; CHECK: ret
define <2 x float> @test1(<2 x i32> %in) {
+; CHECK-LABEL: test1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: scvtf.2s v0, v0, #4
+; CHECK-NEXT: ret
entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 16.0, float 16.0>
@@ -12,10 +14,11 @@ entry:
}
; Test unsigned conversion.
-; CHECK-LABEL: @test2
-; CHECK: ucvtf.2s v0, v0, #3
-; CHECK: ret
define <2 x float> @test2(<2 x i32> %in) {
+; CHECK-LABEL: test2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ucvtf.2s v0, v0, #3
+; CHECK-NEXT: ret
entry:
%vcvt.i = uitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 8.0, float 8.0>
@@ -23,12 +26,13 @@ entry:
}
; Test which should not fold due to non-power of 2.
-; CHECK-LABEL: @test3
-; CHECK: scvtf.2s v0, v0
-; CHECK: fmov.2s v1, #9.00000000
-; CHECK: fdiv.2s v0, v0, v1
-; CHECK: ret
define <2 x float> @test3(<2 x i32> %in) {
+; CHECK-LABEL: test3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: scvtf.2s v0, v0
+; CHECK-NEXT: fmov.2s v1, #9.00000000
+; CHECK-NEXT: fdiv.2s v0, v0, v1
+; CHECK-NEXT: ret
entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 9.0, float 9.0>
@@ -36,12 +40,13 @@ entry:
}
; Test which should not fold due to power of 2 out of range.
-; CHECK-LABEL: @test4
-; CHECK: scvtf.2s v0, v0
-; CHECK: movi.2s v1, #80, lsl #24
-; CHECK: fdiv.2s v0, v0, v1
-; CHECK: ret
define <2 x float> @test4(<2 x i32> %in) {
+; CHECK-LABEL: test4:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: scvtf.2s v0, v0
+; CHECK-NEXT: movi.2s v1, #80, lsl #24
+; CHECK-NEXT: fdiv.2s v0, v0, v1
+; CHECK-NEXT: ret
entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
@@ -49,10 +54,11 @@ entry:
}
; Test case where const is max power of 2 (i.e., 2^32).
-; CHECK-LABEL: @test5
-; CHECK: scvtf.2s v0, v0, #32
-; CHECK: ret
define <2 x float> @test5(<2 x i32> %in) {
+; CHECK-LABEL: test5:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: scvtf.2s v0, v0, #32
+; CHECK-NEXT: ret
entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
@@ -60,10 +66,11 @@ entry:
}
; Test quadword.
-; CHECK-LABEL: @test6
-; CHECK: scvtf.4s v0, v0, #2
-; CHECK: ret
define <4 x float> @test6(<4 x i32> %in) {
+; CHECK-LABEL: test6:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: scvtf.4s v0, v0, #2
+; CHECK-NEXT: ret
entry:
%vcvt.i = sitofp <4 x i32> %in to <4 x float>
%div.i = fdiv <4 x float> %vcvt.i, <float 4.0, float 4.0, float 4.0, float 4.0>
@@ -71,44 +78,48 @@ entry:
}
; Test unsigned i16 to float
-; CHECK-LABEL: @test7
-; CHECK: ushll.4s v0, v0, #0
-; CHECK: ucvtf.4s v0, v0, #1
-; CHECK: ret
define <4 x float> @test7(<4 x i16> %in) {
+; CHECK-LABEL: test7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: ucvtf.4s v0, v0, #1
+; CHECK-NEXT: ret
%conv = uitofp <4 x i16> %in to <4 x float>
%shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
ret <4 x float> %shift
}
; Test signed i16 to float
-; CHECK-LABEL: @test8
-; CHECK: sshll.4s v0, v0, #0
-; CHECK: scvtf.4s v0, v0, #2
-; CHECK: ret
define <4 x float> @test8(<4 x i16> %in) {
+; CHECK-LABEL: test8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: scvtf.4s v0, v0, #2
+; CHECK-NEXT: ret
%conv = sitofp <4 x i16> %in to <4 x float>
%shift = fdiv <4 x float> %conv, <float 4.0, float 4.0, float 4.0, float 4.0>
ret <4 x float> %shift
}
; Can't convert i64 to float.
-; CHECK-LABEL: @test9
-; CHECK: ucvtf.2d v0, v0
-; CHECK: fcvtn v0.2s, v0.2d
-; CHECK: movi.2s v1, #64, lsl #24
-; CHECK: fdiv.2s v0, v0, v1
-; CHECK: ret
define <2 x float> @test9(<2 x i64> %in) {
+; CHECK-LABEL: test9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.2d v0, v0
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: movi.2s v1, #64, lsl #24
+; CHECK-NEXT: fdiv.2s v0, v0, v1
+; CHECK-NEXT: ret
%conv = uitofp <2 x i64> %in to <2 x float>
%shift = fdiv <2 x float> %conv, <float 2.0, float 2.0>
ret <2 x float> %shift
}
-; CHECK-LABEL: @test10
-; CHECK: ucvtf.2d v0, v0, #1
-; CHECK: ret
define <2 x double> @test10(<2 x i64> %in) {
+; CHECK-LABEL: test10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.2d v0, v0, #1
+; CHECK-NEXT: ret
%conv = uitofp <2 x i64> %in to <2 x double>
%shift = fdiv <2 x double> %conv, <double 2.0, double 2.0>
ret <2 x double> %shift
diff --git a/llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll b/llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
index f3447b18ec3db..7a073cad5d206 100644
--- a/llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
+++ b/llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
@x = common dso_local global i128 0
diff --git a/llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
index e43c8e9dfedbd..a353ee0aa551d 100644
--- a/llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
@@ -1,15 +1,19 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; FADD
define double @fadda_nxv8f64(double %init, <vscale x 8 x double> %a) {
-; CHECK-LABEL: fadda_nxv8f64
-; CHECK: ptrue p0.d
-; CHECK-NEXT: fadda d0, p0, d0, z1.d
-; CHECK-NEXT: fadda d0, p0, d0, z2.d
-; CHECK-NEXT: fadda d0, p0, d0, z3.d
-; CHECK-NEXT: fadda d0, p0, d0, z4.d
-; CHECK-NEXT: ret
+; CHECK-LABEL: fadda_nxv8f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fadda d0, p0, d0, z1.d
+; CHECK-NEXT: fadda d0, p0, d0, z2.d
+; CHECK-NEXT: fadda d0, p0, d0, z3.d
+; CHECK-NEXT: fadda d0, p0, d0, z4.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
%res = call double @llvm.vector.reduce.fadd.nxv8f64(double %init, <vscale x 8 x double> %a)
ret double %res
}
@@ -18,11 +22,12 @@ define double @fadda_nxv8f64(double %init, <vscale x 8 x double> %a) {
define float @faddv_nxv8f32(float %init, <vscale x 8 x float> %a) {
; CHECK-LABEL: faddv_nxv8f32:
-; CHECK: fadd z1.s, z1.s, z2.s
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: faddv s1, p0, z1.s
-; CHECK-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: fadd z1.s, z1.s, z2.s
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: faddv s1, p0, z1.s
+; CHECK-NEXT: fadd s0, s0, s1
+; CHECK-NEXT: ret
%res = call fast float @llvm.vector.reduce.fadd.nxv8f32(float %init, <vscale x 8 x float> %a)
ret float %res
}
@@ -31,12 +36,14 @@ define float @faddv_nxv8f32(float %init, <vscale x 8 x float> %a) {
define double @fmaxv_nxv8f64(<vscale x 8 x double> %a) {
; CHECK-LABEL: fmaxv_nxv8f64:
-; CHECK: ptrue p0.d
-; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z3.d
-; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT: fmaxnmv d0, p0, z0.d
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: fmaxnmv d0, p0, z0.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
%res = call double @llvm.vector.reduce.fmax.nxv8f64(<vscale x 8 x double> %a)
ret double %res
}
@@ -45,10 +52,12 @@ define double @fmaxv_nxv8f64(<vscale x 8 x double> %a) {
define half @fminv_nxv16f16(<vscale x 16 x half> %a) {
; CHECK-LABEL: fminv_nxv16f16:
-; CHECK: ptrue p0.h
-; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT: fminnmv h0, p0, z0.h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: fminnmv h0, p0, z0.h
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT: ret
%res = call half @llvm.vector.reduce.fmin.nxv16f16(<vscale x 16 x half> %a)
ret half %res
}
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