[PATCH] D109848: [SDAG] Disable expansion of FMINNUM/FMAXNUM to SELECT_CC for vector operands

[Sridhar Gopinath via Phabricator via llvm-commits]

sridhar_gopinath created this revision.
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FMINNUM/FMAXNUM is expanded to SELECT_CC when there are no-NaNs. But this expansion is
incorrect for vector operands. This fix disables this expansion for vectors.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109848

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -7062,13 +7062,13 @@
     }
   }
 
-  // If none of the above worked, but there are no NaNs, then expand to
-  // a compare/select sequence.  This is required for correctness since
-  // InstCombine might have canonicalized a fcmp+select sequence to a
+  // If none of the above worked for scalar operands, but there are no NaNs,
+  // then expand to a compare/select sequence.  This is required for correctness
+  // since InstCombine might have canonicalized a fcmp+select sequence to a
   // FMINNUM/FMAXNUM node.  If we were to fall through to the default
   // expansion to libcall, we might introduce a link-time dependency
   // on libm into a file that originally did not have one.
-  if (Node->getFlags().hasNoNaNs()) {
+  if (!VT.isVector() && Node->getFlags().hasNoNaNs()) {
     ISD::CondCode Pred =
         Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
     SDValue Op1 = Node->getOperand(0);


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