[PATCH] D109827: AArch64: use ldp/stp for 128-bit atomic load/store with v8.4

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17689
+           LI->getAlignment() >= 16;
+  else if (auto SI = dyn_cast<StoreInst>(I))
+    return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128 &&
----------------
might as well make this an if?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1029
+  MachineOperand &RHSOp1 = RHS->getOperand(1);
+  if (!RHSOp1.isCImm() || RHSOp1.getCImm()->getBitWidth() > 64)
+    return;
----------------
I think `mi_match` could really simplify this function.

```
if (mi_match(Root, MRI, m_GPtrAdd(m_Reg(NewBase), m_ICst(NewOffset))) && isShiftedInt<7, 3>(NewOffset))) {
  Base = NewBase;
  Offset = NewOffset;
}
```

... But I'm not sure about the >64 bit widths.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109827/new/

https://reviews.llvm.org/D109827