[PATCH] D109146: [AArch64][SVE] Replace fmul and fadd LLVM IR instrinsics with fmul and fadd
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 15 07:18:41 PDT 2021
david-arm added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:700
+ IntrinsicInst &II) {
+ if (match(II.getOperand(0),
+ m_Intrinsic<Intrinsic::aarch64_sve_ptrue>(
----------------
You could restructure this as:
auto BinOpCode = intrinsicIDToBinOpCode(II.getIntrinsicID());
if (BinOpCode == Instruction::BinaryOpsEnd ||
!match(...))
return None;
IRBuilder<> Builder(II.getContext());
...
return IC.replaceInstUsesWith
If you agree that looks better?
================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:855
return instCombineSVEVectorMul(IC, II);
+ case Intrinsic::aarch64_sve_fadd:
+ return instCombineSVEVectorBinOp(IC, II);
----------------
Since we're doing this for fadd shall we also do this for fsub too? It's just literally adding another case statement I think.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109146/new/
https://reviews.llvm.org/D109146
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