[PATCH] D109827: AArch64: use ldp/stp for 128-bit atomic load/store with v8.4

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
t.p.northover added a reviewer: paquette.
Herald added subscribers: hiraditya, kristof.beyls, mcrosier.
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Prior to v8.4a[*] the only way to get a 128-bit atomic load or store was via `ldxp`/`stxp` (or `casp`), which is not only inefficient but outright impossible without write access. So v8.4a extended the memory model so that any 16-byte operation aligned to 16 bytes (as all LLVM atomic load/stores must be) is atomic.

This patch implements ISel for these instructions in both SDAG and GISel. In both cases we go for `ldp`/`stp` implementations since atomics are much more likely to be GPR-based operations.


https://reviews.llvm.org/D109827

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/atomic-ops-lse.ll

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