[PATCH] D109631: [HardwareLoops] Loop guard intrinsic to recognise zext

[Sherwin via Phabricator via llvm-commits]

sherwin-dc added a comment.

@dmgreen would this test case suffice or should I add a ARM test that compiles to a WLS loop?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D109631/new/

https://reviews.llvm.org/D109631