[PATCH] D109515: [AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG
Anton Afanasyev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 14 23:16:05 PDT 2021
anton-afanasyev added inline comments.
================
Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:151
+ // 2. phi node(and loop handling)
// ...
return false;
----------------
anton-afanasyev wrote:
> lebedev.ri wrote:
> > sdiv, srem; see b289dc530632613edb3eb067895c1981cb77ccd0.
> Ok, added to todo.
Hi @lebedev.ri, @spatel , according to this patch rGb289dc530632, sdiv/srem (as well as udiv/urem) instrs are guarded with trunc/ext wherever it's possible. So it looks like support them here in AIC is redundant as we get always `MinBitWidth == OrigBitWidth` after correlated value propagation.
So I'm leaning towards reverting this patch. What do you think?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D109515/new/
https://reviews.llvm.org/D109515
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