[PATCH] D109573: [AArch64] NFC: Use 'asm' in SIMDScalarCPY
Cullen Rhodes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 14 01:27:08 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rG742cf3996ed9: [AArch64] NFC: Use 'asm' in SIMDScalarCPY (authored by c-rhodes).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109573/new/
https://reviews.llvm.org/D109573
Files:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5253,7 +5253,7 @@
// AdvSIMD scalar CPY instruction
//----------------------------------------------------------------------------
-defm CPY : SIMDScalarCPY<"cpy">;
+defm CPY : SIMDScalarCPY<"mov">;
//----------------------------------------------------------------------------
// AdvSIMD scalar pairwise instructions
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -7658,8 +7658,8 @@
//----------------------------------------------------------------------------
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
- string kind, Operand idxtype>
- : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
+ string asm, string kind, Operand idxtype>
+ : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), asm,
"{\t$dst, $src" # kind # "$idx" #
"|\t$dst, $src$idx}", "", []>,
Sched<[WriteV]> {
@@ -7679,22 +7679,22 @@
multiclass SIMDScalarCPY<string asm> {
- def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
+ def i8 : BaseSIMDScalarCPY<FPR8, V128, asm, ".b", VectorIndexB> {
bits<4> idx;
let Inst{20-17} = idx;
let Inst{16} = 1;
}
- def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
+ def i16 : BaseSIMDScalarCPY<FPR16, V128, asm, ".h", VectorIndexH> {
bits<3> idx;
let Inst{20-18} = idx;
let Inst{17-16} = 0b10;
}
- def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
+ def i32 : BaseSIMDScalarCPY<FPR32, V128, asm, ".s", VectorIndexS> {
bits<2> idx;
let Inst{20-19} = idx;
let Inst{18-16} = 0b100;
}
- def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
+ def i64 : BaseSIMDScalarCPY<FPR64, V128, asm, ".d", VectorIndexD> {
bits<1> idx;
let Inst{20} = idx;
let Inst{19-16} = 0b1000;
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