[PATCH] D109671: [AMDGPU] Add BFE pattern matches for constrained shifts.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

abinavpp added a comment.

I think we need the constrained shift pattern to be of the form (srl (shl $src,
(and (sub 32, $width), 31)), (and (sub 32, $width), 31)), which, on $width = 0,
will evaluate to (srl (shl $src, 32), 32) like the original pattern.

I wrote the (sub 0, $width) version since inst-combine, on visiting (and (sub
32, $width), 31), transforms the `sub` using SimplifyDemandedInstructionBits()
to (sub 0, $width). You can see this in the compilation of
https://github.com/RadeonOpenCompute/ROCm/issues/989 's test.

I'm not sure if there's a reasonable way for inst-combine's visitAnd() to stop
doing this so that we can match the BFE pattern correctly.


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https://reviews.llvm.org/D109671