[PATCH] D108795: [PowerPC] Fix issue with lowering byval parameters.
Amy Kwan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 13 18:31:10 PDT 2021
amyk added inline comments.
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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:4331
+static SDValue StoreWithOffset(SelectionDAG &DAG, SDValue Val, SDValue Arg,
+ const Argument *FuncArg, uint64_t Offset,
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Can we add documentation to this function?
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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:4491
- } else {
- // For sizes that don't fit a truncating store (3, 5, 6, 7),
- // store the whole register as-is to the parameter save area
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Might be a silly question, but since it looks like the code for `ObjSize == [1|2|4]` looks like it is still the same, does it make sense for the switch to be in the else case for 3,5,6,7?
Or is it a preference to just transform the whole thing as a switch (like what you've done in the patch)? I'm just wondering as it kind of looks like the code in the cases are fairly repetitive for some of the cases.
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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:4506
+ break;
+ case 3: {
+ // i24 = i16 + i8
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Question: I just wanted to check whether or not using `Arg` in cases 3/5/6/7 is expected, or if it is supposed to be frame index like in the code before?
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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:4519
+ break;
+ case 5:
+ // i40 = i32 + i8
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nit: It looks like for cases 3 and 6, there are `{ }` surrounding the case statements. It may be good to put them around 5 and 7 for consistency.
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Comment at: llvm/test/CodeGen/PowerPC/ppc64-byval-multi-store.ll:3
+; RUN: llc -verify-machineinstrs --mtriple powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P8LE
+; RUN: llc -verify-machineinstrs --mtriple powerpc64le-unknown-linux-gnu \
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nit: Indenting (for here and other lines)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108795/new/
https://reviews.llvm.org/D108795
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