[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:2789
+    const TargetRegisterClass *RC = RI.getRegClassForReg(*MRI, DstReg);
+    bool IsVectorRegCopy = RI.hasVectorRegisters(RC);
+    unsigned NewOpc =
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This logically doesn't flow right. This shouldn't be checking hasVectorRegisters, and just use isVGPR. You override this decision later with the AGPR class


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  https://reviews.llvm.org/D109300/new/

https://reviews.llvm.org/D109300