[PATCH] D109706: [ARM] Allow smaller VMOVL in tail predicated loops

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, ostannard, simon_tatham, NickGuy.
Herald added subscribers: hiraditya, kristof.beyls.
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This allows VMOVL in tail predicated loops so long as the the vector size the VMOVL is extending into is less than or equal to the size of the VCTP in the tail predicated loop. There cases represent a sign-extend-inreg (or zero-extend-inreg), which needn't block tail predication as in https://godbolt.org/z/hdTsEbx8Y.

For this a vecsize has been added to the TSFlag bits of MVE instructions, which stores the size of the elements that the MVE instruction operates on. In the case of multiple size (such as a MVE_VMOVLs8bh that extends from i8 to i16, the largest size was be chosen).  The sizes are encoded as 00 = i8, 01 = i16, 10 = i32 and 11 = i64, which often (but not always) comes from the instruction encoding directly. A unit test was added, and although only a subset of the vecsizes are currently used, the rest should be useful for other cases.


https://reviews.llvm.org/D109706

Files:
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
  llvm/test/CodeGen/Thumb2/mve-vmovlloop.ll
  llvm/unittests/Target/ARM/MachineInstrTest.cpp

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