[llvm] f293361 - [RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 13 01:23:21 PDT 2021
Author: Jim Lin
Date: 2021-09-13T16:24:15+08:00
New Revision: f29336104d8f5cc023d3cc55cbcc1ea401c46c5d
URL: https://github.com/llvm/llvm-project/commit/f29336104d8f5cc023d3cc55cbcc1ea401c46c5d
DIFF: https://github.com/llvm/llvm-project/commit/f29336104d8f5cc023d3cc55cbcc1ea401c46c5d.diff
LOG: [RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension
Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension for consistency
Reviewed By: HsiangKai, asb
Differential Revision: https://reviews.llvm.org/D108187
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b2aa585a2ba33..ddf07b808d038 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2074,19 +2074,20 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
- clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
- clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
- clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
- clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
- clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
- clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
- clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
- clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
- clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
- clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
- clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
- clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
- clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+ clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
+ clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
+ clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
+ clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
+ clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
+ clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
+ clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
+ clearFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
+ clearFeatureBits(RISCV::FeatureStdExtZbproposedc,
+ "experimental-zbproposedc");
+ clearFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
+ clearFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
+ clearFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
+ clearFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
while (!Arch.empty()) {
@@ -2120,32 +2121,32 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
StringRef Ext =
Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
if (Ext == "zba")
- setFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+ setFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
else if (Ext == "zbb")
- setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+ setFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
else if (Ext == "zbc")
- setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+ setFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
else if (Ext == "zbe")
- setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+ setFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
else if (Ext == "zbf")
- setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+ setFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
else if (Ext == "zbm")
- setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+ setFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
else if (Ext == "zbp")
- setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+ setFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
else if (Ext == "zbproposedc")
- setFeatureBits(RISCV::FeatureExtZbproposedc,
+ setFeatureBits(RISCV::FeatureStdExtZbproposedc,
"experimental-zbproposedc");
else if (Ext == "zbr")
- setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+ setFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
else if (Ext == "zbs")
- setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+ setFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
else if (Ext == "zbt")
- setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+ setFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
else if (Ext == "zfh")
- setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+ setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
else if (Ext == "zvamo")
- setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+ setFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
else if (Ext == "zvlsseg")
setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
else
@@ -2194,31 +2195,31 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtV))
formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
- if (getFeatureBits(RISCV::FeatureExtZfh))
+ if (getFeatureBits(RISCV::FeatureStdExtZfh))
formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
- if (getFeatureBits(RISCV::FeatureExtZba))
+ if (getFeatureBits(RISCV::FeatureStdExtZba))
formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbb))
+ if (getFeatureBits(RISCV::FeatureStdExtZbb))
formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbc))
+ if (getFeatureBits(RISCV::FeatureStdExtZbc))
formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbe))
+ if (getFeatureBits(RISCV::FeatureStdExtZbe))
formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbf))
+ if (getFeatureBits(RISCV::FeatureStdExtZbf))
formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbm))
+ if (getFeatureBits(RISCV::FeatureStdExtZbm))
formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbp))
+ if (getFeatureBits(RISCV::FeatureStdExtZbp))
formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbproposedc))
+ if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbr))
+ if (getFeatureBits(RISCV::FeatureStdExtZbr))
formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbs))
+ if (getFeatureBits(RISCV::FeatureStdExtZbs))
formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZbt))
+ if (getFeatureBits(RISCV::FeatureStdExtZbt))
formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
- if (getFeatureBits(RISCV::FeatureExtZvamo))
+ if (getFeatureBits(RISCV::FeatureStdExtZvamo))
formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str();
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 504a78d91f321..d5cdac569d79c 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -449,7 +449,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
}
- if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] &&
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtZbproposedc] &&
STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
LLVM_DEBUG(
dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index af0434e9a7834..a6c469830ec68 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -165,7 +165,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
// the end of the sequence.
- if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureExtZba]) {
+ if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
// Try replacing upper bits with 1.
uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
TmpSeq.clear();
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 13c4b84aa3008..fd6e49d02c22f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -64,31 +64,31 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
Arch += "_b0p93";
if (STI.hasFeature(RISCV::FeatureStdExtV))
Arch += "_v0p10";
- if (STI.hasFeature(RISCV::FeatureExtZfh))
+ if (STI.hasFeature(RISCV::FeatureStdExtZfh))
Arch += "_zfh0p1";
- if (STI.hasFeature(RISCV::FeatureExtZba))
+ if (STI.hasFeature(RISCV::FeatureStdExtZba))
Arch += "_zba0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbb))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbb))
Arch += "_zbb0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbc))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbc))
Arch += "_zbc0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbe))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbe))
Arch += "_zbe0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbf))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbf))
Arch += "_zbf0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbm))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbm))
Arch += "_zbm0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbp))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbp))
Arch += "_zbp0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
Arch += "_zbproposedc0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbr))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbr))
Arch += "_zbr0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbs))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbs))
Arch += "_zbs0p93";
- if (STI.hasFeature(RISCV::FeatureExtZbt))
+ if (STI.hasFeature(RISCV::FeatureStdExtZbt))
Arch += "_zbt0p93";
- if (STI.hasFeature(RISCV::FeatureExtZvamo))
+ if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
Arch += "_zvamo0p10";
if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
Arch += "_zvlsseg0p10";
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 284ff2f5ad51a..ae6c6b252d22d 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -41,12 +41,12 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
-def FeatureExtZfh
+def FeatureStdExtZfh
: SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
- AssemblerPredicate<(all_of FeatureExtZfh),
+ AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
def FeatureStdExtC
@@ -56,105 +56,105 @@ def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
-def FeatureExtZba
+def FeatureStdExtZba
: SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
"'Zba' (Address calculation 'B' Instructions)">;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
- AssemblerPredicate<(all_of FeatureExtZba),
+ AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address calculation 'B' Instructions)">;
def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
-def FeatureExtZbb
+def FeatureStdExtZbb
: SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
"'Zbb' (Base 'B' Instructions)">;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
- AssemblerPredicate<(all_of FeatureExtZbb),
+ AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Base 'B' Instructions)">;
-def FeatureExtZbc
+def FeatureStdExtZbc
: SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true",
"'Zbc' (Carry-Less 'B' Instructions)">;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
- AssemblerPredicate<(all_of FeatureExtZbc),
+ AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less 'B' Instructions)">;
-def FeatureExtZbe
+def FeatureStdExtZbe
: SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
"'Zbe' (Extract-Deposit 'B' Instructions)">;
def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
- AssemblerPredicate<(all_of FeatureExtZbe),
+ AssemblerPredicate<(all_of FeatureStdExtZbe),
"'Zbe' (Extract-Deposit 'B' Instructions)">;
-def FeatureExtZbf
+def FeatureStdExtZbf
: SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
"'Zbf' (Bit-Field 'B' Instructions)">;
def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
- AssemblerPredicate<(all_of FeatureExtZbf),
+ AssemblerPredicate<(all_of FeatureStdExtZbf),
"'Zbf' (Bit-Field 'B' Instructions)">;
-def FeatureExtZbm
+def FeatureStdExtZbm
: SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
"'Zbm' (Matrix 'B' Instructions)">;
def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
- AssemblerPredicate<(all_of FeatureExtZbm),
+ AssemblerPredicate<(all_of FeatureStdExtZbm),
"'Zbm' (Matrix 'B' Instructions)">;
-def FeatureExtZbp
+def FeatureStdExtZbp
: SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
"'Zbp' (Permutation 'B' Instructions)">;
def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
- AssemblerPredicate<(all_of FeatureExtZbp),
+ AssemblerPredicate<(all_of FeatureStdExtZbp),
"'Zbp' (Permutation 'B' Instructions)">;
-def FeatureExtZbr
+def FeatureStdExtZbr
: SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true",
"'Zbr' (Polynomial Reduction 'B' Instructions)">;
def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
- AssemblerPredicate<(all_of FeatureExtZbr),
+ AssemblerPredicate<(all_of FeatureStdExtZbr),
"'Zbr' (Polynomial Reduction 'B' Instructions)">;
-def FeatureExtZbs
+def FeatureStdExtZbs
: SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true",
"'Zbs' (Single-Bit 'B' Instructions)">;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
- AssemblerPredicate<(all_of FeatureExtZbs),
+ AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit 'B' Instructions)">;
-def FeatureExtZbt
+def FeatureStdExtZbt
: SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
"'Zbt' (Ternary 'B' Instructions)">;
def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
- AssemblerPredicate<(all_of FeatureExtZbt),
+ AssemblerPredicate<(all_of FeatureStdExtZbt),
"'Zbt' (Ternary 'B' Instructions)">;
// Some instructions belong to both the basic and the permutation
// subextensions. They should be enabled if either has been specified.
def HasStdExtZbbOrZbp
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
- AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp),
+ AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
"'Zbb' (Base 'B' Instructions) or "
"'Zbp' (Permutation 'B' Instructions)">;
-def FeatureExtZbproposedc
+def FeatureStdExtZbproposedc
: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
"'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
- AssemblerPredicate<(all_of FeatureExtZbproposedc),
+ AssemblerPredicate<(all_of FeatureStdExtZbproposedc),
"'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
def FeatureStdExtB
: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
"'B' (Bit Manipulation Instructions)",
- [FeatureExtZba,
- FeatureExtZbb,
- FeatureExtZbc,
- FeatureExtZbe,
- FeatureExtZbf,
- FeatureExtZbm,
- FeatureExtZbp,
- FeatureExtZbr,
- FeatureExtZbs,
- FeatureExtZbt]>;
+ [FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbe,
+ FeatureStdExtZbf,
+ FeatureStdExtZbm,
+ FeatureStdExtZbp,
+ FeatureStdExtZbr,
+ FeatureStdExtZbs,
+ FeatureStdExtZbt]>;
def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
AssemblerPredicate<(all_of FeatureStdExtB),
"'B' (Bit Manipulation Instructions)">;
@@ -181,12 +181,12 @@ def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
"'Zvlsseg' (Vector segment load/store instructions)">;
-def FeatureExtZvamo
+def FeatureStdExtZvamo
: SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
"'Zvamo' (Vector AMO Operations)",
[FeatureStdExtV]>;
def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
- AssemblerPredicate<(all_of FeatureExtZvamo),
+ AssemblerPredicate<(all_of FeatureStdExtZvamo),
"'Zvamo' (Vector AMO Operations)">;
def Feature64Bit
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