[PATCH] D109665: [AArch64][SVE] Add patterns to generate ADR instruction

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem created this revision.
mnadeem added reviewers: david-arm, sdesmalen, paulwalker-arm.
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Patterns for:

- adr z0.s, [z0.s, z0.s, lsl #<shift>]
- adr z0.d, [z0.d, z0.d, lsl #<shift>]
- adr z0.d, [z0.d, z0.d, uxtw #<shift>]
- adr z0.d, [z0.d, z0.d, sxtw #<shift>]

Did not add a pattern for

- adr z0.s, [z0.s, z0.s]
- adr z0.d, [z0.d, z0.d]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109665

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-gep.ll

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