[llvm] fb7fbe4 - [NFC][SVE] Precommit tests for adr instruction

Usman Nadeem via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 12 15:07:00 PDT 2021


Author: Usman Nadeem
Date: 2021-09-12T15:06:28-07:00
New Revision: fb7fbe4314f5e00ee47f87cf0b0fa56edd801236

URL: https://github.com/llvm/llvm-project/commit/fb7fbe4314f5e00ee47f87cf0b0fa56edd801236
DIFF: https://github.com/llvm/llvm-project/commit/fb7fbe4314f5e00ee47f87cf0b0fa56edd801236.diff

LOG: [NFC][SVE] Precommit tests for adr instruction

Change-Id: I8148481a5ce3b721113327cc9b684f091cae5a8d

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/sve-gep.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/sve-gep.ll b/llvm/test/CodeGen/AArch64/sve-gep.ll
index bfa4f90d35ab..0fee23bfac4c 100644
--- a/llvm/test/CodeGen/AArch64/sve-gep.ll
+++ b/llvm/test/CodeGen/AArch64/sve-gep.ll
@@ -74,8 +74,8 @@ define <vscale x 2 x i8*> @scalable_of_fixed_2(<vscale x 2 x i8*> %base) {
   ret <vscale x 2 x i8*> %d
 }
 
-define <vscale x 2 x i8*> @scalable_of_fixed_3(i8* %base, <vscale x 2 x i64> %idx) {
-; CHECK-LABEL: scalable_of_fixed_3:
+define <vscale x 2 x i8*> @scalable_of_fixed_3_i8(i8* %base, <vscale x 2 x i64> %idx) {
+; CHECK-LABEL: scalable_of_fixed_3_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z1.d, x0
 ; CHECK-NEXT:    add z0.d, z1.d, z0.d
@@ -84,8 +84,41 @@ define <vscale x 2 x i8*> @scalable_of_fixed_3(i8* %base, <vscale x 2 x i64> %id
   ret <vscale x 2 x i8*> %d
 }
 
-define <vscale x 2 x i8*> @scalable_of_fixed_4(i8* %base, <vscale x 2 x i32> %idx) {
-; CHECK-LABEL: scalable_of_fixed_4:
+define <vscale x 2 x i16*> @scalable_of_fixed_3_i16(i16* %base, <vscale x 2 x i64> %idx) {
+; CHECK-LABEL: scalable_of_fixed_3_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.d, z0.d, #1
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i16, i16* %base, <vscale x 2 x i64> %idx
+  ret <vscale x 2 x i16*> %d
+}
+
+define <vscale x 2 x i32*> @scalable_of_fixed_3_i32(i32* %base, <vscale x 2 x i64> %idx) {
+; CHECK-LABEL: scalable_of_fixed_3_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.d, z0.d, #2
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i32, i32* %base, <vscale x 2 x i64> %idx
+  ret <vscale x 2 x i32*> %d
+}
+
+define <vscale x 2 x i64*> @scalable_of_fixed_3_i64(i64* %base, <vscale x 2 x i64> %idx) {
+; CHECK-LABEL: scalable_of_fixed_3_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.d, z0.d, #3
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i64, i64* %base, <vscale x 2 x i64> %idx
+  ret <vscale x 2 x i64*> %d
+}
+
+define <vscale x 2 x i8*> @scalable_of_fixed_4_i8(i8* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_4_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
@@ -96,6 +129,97 @@ define <vscale x 2 x i8*> @scalable_of_fixed_4(i8* %base, <vscale x 2 x i32> %id
   ret <vscale x 2 x i8*> %d
 }
 
+define <vscale x 2 x i16*> @scalable_of_fixed_4_i16(i16* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_4_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
+; CHECK-NEXT:    lsl z0.d, z0.d, #1
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i16, i16* %base, <vscale x 2 x i32> %idx
+  ret <vscale x 2 x i16*> %d
+}
+
+define <vscale x 2 x i32*> @scalable_of_fixed_4_i32(i32* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_4_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
+; CHECK-NEXT:    lsl z0.d, z0.d, #2
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i32, i32* %base, <vscale x 2 x i32> %idx
+  ret <vscale x 2 x i32*> %d
+}
+
+define <vscale x 2 x i64*> @scalable_of_fixed_4_i64(i64* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_4_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
+; CHECK-NEXT:    lsl z0.d, z0.d, #3
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %d = getelementptr i64, i64* %base, <vscale x 2 x i32> %idx
+  ret <vscale x 2 x i64*> %d
+}
+
+define <vscale x 2 x i8*> @scalable_of_fixed_5(i8* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    and z0.d, z0.d, #0xffffffff
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %idxZext = zext <vscale x 2 x i32> %idx to <vscale x 2 x i64>
+  %d = getelementptr i8, i8* %base, <vscale x 2 x i64> %idxZext
+  ret <vscale x 2 x i8*> %d
+}
+
+define <vscale x 2 x i16*> @scalable_of_fixed_5_i16(i16* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_5_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and z0.d, z0.d, #0xffffffff
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    lsl z0.d, z0.d, #1
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %idxZext = zext <vscale x 2 x i32> %idx to <vscale x 2 x i64>
+  %d = getelementptr i16, i16* %base, <vscale x 2 x i64> %idxZext
+  ret <vscale x 2 x i16*> %d
+}
+
+define <vscale x 2 x i32*> @scalable_of_fixed_5_i32(i32* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_5_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and z0.d, z0.d, #0xffffffff
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    lsl z0.d, z0.d, #2
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %idxZext = zext <vscale x 2 x i32> %idx to <vscale x 2 x i64>
+  %d = getelementptr i32, i32* %base, <vscale x 2 x i64> %idxZext
+  ret <vscale x 2 x i32*> %d
+}
+
+
+define <vscale x 2 x i64*> @scalable_of_fixed_5_i64(i64* %base, <vscale x 2 x i32> %idx) {
+; CHECK-LABEL: scalable_of_fixed_5_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and z0.d, z0.d, #0xffffffff
+; CHECK-NEXT:    mov z1.d, x0
+; CHECK-NEXT:    lsl z0.d, z0.d, #3
+; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    ret
+  %idxZext = zext <vscale x 2 x i32> %idx to <vscale x 2 x i64>
+  %d = getelementptr i64, i64* %base, <vscale x 2 x i64> %idxZext
+  ret <vscale x 2 x i64*> %d
+}
+
 define <vscale x 2 x <vscale x 2 x i64>*> @scalable_of_scalable_1(<vscale x 2 x i64>* %base) {
 ; CHECK-LABEL: scalable_of_scalable_1:
 ; CHECK:       // %bb.0:


        


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