[PATCH] D109657: [SystemZ] Accept plain register name where an address is expected.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
jonpa added a reviewer: uweigand.
Herald added subscribers: ctetreau, hiraditya.
jonpa requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Allow an address to be written as just a single (base) register in assembly.

Example: 'lg %r0, 0(%r1)' and 'lg %r0, %r1' are equivalent.

This patch is not checking the expected kind of address (MemKind) or HasLength / HasVectorIndex - would that be better?


https://reviews.llvm.org/D109657

Files:
  llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
  llvm/test/MC/SystemZ/insn-good.s


Index: llvm/test/MC/SystemZ/insn-good.s
===================================================================
--- llvm/test/MC/SystemZ/insn-good.s
+++ llvm/test/MC/SystemZ/insn-good.s
@@ -5,6 +5,7 @@
 #CHECK: a	%r0, 4095               # encoding: [0x5a,0x00,0x0f,0xff]
 #CHECK: a	%r0, 0(%r1)             # encoding: [0x5a,0x00,0x10,0x00]
 #CHECK: a	%r0, 0(%r15)            # encoding: [0x5a,0x00,0xf0,0x00]
+#CHECK: a	%r0, 0(%r15)            # encoding: [0x5a,0x00,0xf0,0x00]
 #CHECK: a	%r0, 4095(%r1,%r15)     # encoding: [0x5a,0x01,0xff,0xff]
 #CHECK: a	%r0, 4095(%r15,%r1)     # encoding: [0x5a,0x0f,0x1f,0xff]
 #CHECK: a	%r15, 0                 # encoding: [0x5a,0xf0,0x00,0x00]
@@ -20,6 +21,7 @@
 	a	%r0, 4095
 	a	%r0, 0(%r1)
 	a	%r0, 0(%r15)
+	a	%r0, %r15
 	a	%r0, 4095(%r1,%r15)
 	a	%r0, 4095(%r15,%r1)
 	a	%r15, 0
@@ -52,6 +54,7 @@
 #CHECK: adb	%f0, 4095               # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1a]
 #CHECK: adb	%f0, 0(%r1)             # encoding: [0xed,0x00,0x10,0x00,0x00,0x1a]
 #CHECK: adb	%f0, 0(%r15)            # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1a]
+#CHECK: adb	%f0, 0(%r15)            # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1a]
 #CHECK: adb	%f0, 4095(%r1,%r15)     # encoding: [0xed,0x01,0xff,0xff,0x00,0x1a]
 #CHECK: adb	%f0, 4095(%r15,%r1)     # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1a]
 #CHECK: adb	%f15, 0                 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1a]
@@ -60,6 +63,7 @@
 	adb	%f0, 4095
 	adb	%f0, 0(%r1)
 	adb	%f0, 0(%r15)
+	adb	%f0, %r15
 	adb	%f0, 4095(%r1,%r15)
 	adb	%f0, 4095(%r15,%r1)
 	adb	%f15, 0
@@ -9433,6 +9437,7 @@
 #CHECK: lg	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x04]
 #CHECK: lg	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x04]
 #CHECK: lg	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x04]
+#CHECK: lg	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x04]
 #CHECK: lg	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x04]
 #CHECK: lg	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x04]
 #CHECK: lg	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x04]
@@ -9444,6 +9449,7 @@
 	lg	%r0, 524287
 	lg	%r0, 0(%r1)
 	lg	%r0, 0(%r15)
+	lg	%r0, %r15
 	lg	%r0, 524287(%r1,%r15)
 	lg	%r0, 524287(%r15,%r1)
 	lg	%r15, 0
Index: llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
===================================================================
--- llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -990,15 +990,25 @@
                                     bool &HaveReg2, Register &Reg2,
                                     const MCExpr *&Disp, const MCExpr *&Length,
                                     bool HasLength, bool HasVectorIndex) {
-  // Parse the displacement, which must always be present.
-  if (getParser().parseExpression(Disp))
-    return true;
-
-  // Parse the optional base and index.
   HaveReg1 = false;
   HaveReg2 = false;
   Length = nullptr;
 
+  // Parse a single register as a complete address.
+  if (getLexer().is(AsmToken::Percent)) {
+    if (parseRegister(Reg1))
+      return true;
+    HaveReg1 = true;
+    Disp = MCConstantExpr::create(0, getContext());
+    return false;
+  }
+
+  // Parse the displacement, which at this point must always be present.
+  if (getParser().parseExpression(Disp))
+    return true;
+
+  // Parse the optional base and index.
+  //
   // If we have a scenario as below:
   //   vgef %v0, 0(0), 0
   // This is an example of a "BDVMem" instruction type.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D109657.372114.patch
Type: text/x-patch
Size: 3571 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210912/a6cdc7de/attachment.bin>