[llvm] 7c82db3 - [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE

[Mark Schimmel via llvm-commits]

Author: Mark Schimmel
Date: 2021-09-10T13:04:08-07:00
New Revision: 7c82db3634c1c8c0319816d4bbaa099c7a532b06

URL: https://github.com/llvm/llvm-project/commit/7c82db3634c1c8c0319816d4bbaa099c7a532b06
DIFF: https://github.com/llvm/llvm-project/commit/7c82db3634c1c8c0319816d4bbaa099c7a532b06.diff

LOG: [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
This change improves the code generated for long long addition and subtraction

Differential Revision: https://reviews.llvm.org/D109615

Added: 
    

Modified: 
    llvm/lib/Target/ARC/ARCISelLowering.cpp
    llvm/lib/Target/ARC/ARCInstrInfo.td
    llvm/test/CodeGen/ARC/alu.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
index 7b13f800f2167..588fe5c844817 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -121,6 +121,11 @@ ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SMAX, MVT::i32, Legal);
   setOperationAction(ISD::SMIN, MVT::i32, Legal);
 
+  setOperationAction(ISD::ADDC, MVT::i32, Legal);
+  setOperationAction(ISD::ADDE, MVT::i32, Legal);
+  setOperationAction(ISD::SUBC, MVT::i32, Legal);
+  setOperationAction(ISD::SUBE, MVT::i32, Legal);
+
   // Need barrel shifter.
   setOperationAction(ISD::SHL, MVT::i32, Legal);
   setOperationAction(ISD::SRA, MVT::i32, Legal);

diff  --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td
index 0b7a5a6db24e0..4a0bc5cf74215 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.td
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -328,6 +328,11 @@ defm : MultiPat<mul, MPY_rrr, MPY_rru6, MPY_rrlimm>;
 defm : MultiPat<mulhs, MPYM_rrr, MPYM_rru6, MPYM_rrlimm>;
 defm : MultiPat<mulhu, MPYMU_rrr, MPYMU_rru6, MPYMU_rrlimm>;
 
+defm : MultiPat<addc, ADD_f_rrr, ADD_f_rru6, ADD_f_rrlimm>;
+defm : MultiPat<adde, ADC_f_rrr, ADC_f_rru6, ADC_f_rrlimm>;
+defm : MultiPat<subc, SUB_f_rrr, SUB_f_rru6, SUB_f_rrlimm>;
+defm : MultiPat<sube, SBC_f_rrr, SBC_f_rru6, SBC_f_rrlimm>;
+
 // ---------------------------------------------------------------------------
 // Unary Instruction definitions.
 // ---------------------------------------------------------------------------

diff  --git a/llvm/test/CodeGen/ARC/alu.ll b/llvm/test/CodeGen/ARC/alu.ll
index a5e07636fec08..2315196d427ce 100644
--- a/llvm/test/CodeGen/ARC/alu.ll
+++ b/llvm/test/CodeGen/ARC/alu.ll
@@ -253,3 +253,20 @@ define i64 @muls64(i32 %a, i32 %b) nounwind {
   ret i64 %v
 }
 
+; CHECK-LABEL: long_long_add
+; CHECK:      add.f %r0, %r0, %r2
+; CHECK-NEXT: adc.f %r1, %r1, %r3
+define i64 @long_long_add(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %add = add nsw i64 %a, %b
+  ret i64 %add
+}
+
+; CHECK-LABEL: long_long_sub
+; CHECK:      sub.f %r0, %r0, %r2
+; CHECK-NEXT: sbc.f %r1, %r1, %r3
+define i64 @long_long_sub(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %sub = sub nsw i64 %a, %b
+  ret i64 %sub
+}