[llvm] 2c5590a - [AArch64] Regenerate some test checks. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 10 05:48:25 PDT 2021
Author: David Green
Date: 2021-09-10T13:48:15+01:00
New Revision: 2c5590adfe09283d0c400507be61198b63ce5063
URL: https://github.com/llvm/llvm-project/commit/2c5590adfe09283d0c400507be61198b63ce5063
DIFF: https://github.com/llvm/llvm-project/commit/2c5590adfe09283d0c400507be61198b63ce5063.diff
LOG: [AArch64] Regenerate some test checks. NFC
This updates some mostly update_test_check test files and generates the
check lines with the script, making them more maintainable.
Added:
Modified:
llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
llvm/test/CodeGen/AArch64/build-one-lane.ll
llvm/test/CodeGen/AArch64/dag-combine-select.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64-be-bv.ll b/llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
index 67816d278bce..2117cc6dac66 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
@@ -1,373 +1,502 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64_be--linux-gnu < %s | FileCheck %s
@vec_v8i16 = dso_local global <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
-; CHECK-LABEL: movi_modimm_t1:
define dso_local void @movi_modimm_t1() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t2:
define dso_local void @movi_modimm_t2() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1, lsl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t3:
define dso_local void @movi_modimm_t3() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1, lsl #16
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t4:
define dso_local void @movi_modimm_t4() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1, lsl #24
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t5:
define dso_local void @movi_modimm_t5() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.8h, #1
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t6:
define dso_local void @movi_modimm_t6() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1, lsl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.8h, #1, lsl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t7:
define dso_local void @movi_modimm_t7() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1, msl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t8:
define dso_local void @movi_modimm_t8() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #16
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.4s, #1, msl #16
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t9:
define dso_local void @movi_modimm_t9() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #1
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: movi_modimm_t10:
define dso_local void @movi_modimm_t10() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: movi v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: movi_modimm_t10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: fmov_modimm_t11:
define dso_local void @fmov_modimm_t11() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].4s, #3.00000000
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: fmov_modimm_t11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: fmov v1.4s, #3.00000000
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: fmov_modimm_t12:
define dso_local void @fmov_modimm_t12() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].2d, #0.17968750
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: fmov_modimm_t12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: fmov v1.2d, #0.17968750
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t1:
define dso_local void @mvni_modimm_t1() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t2:
define dso_local void @mvni_modimm_t2() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1, lsl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t3:
define dso_local void @mvni_modimm_t3() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #16
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1, lsl #16
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t4:
define dso_local void @mvni_modimm_t4() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #24
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1, lsl #24
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t5:
define dso_local void @mvni_modimm_t5() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.8h, #1
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t6:
define dso_local void @mvni_modimm_t6() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1, lsl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.8h, #1, lsl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t7:
define dso_local void @mvni_modimm_t7() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #8
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: mvni_modimm_t8:
define dso_local void @mvni_modimm_t8() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #16
- ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: mvni_modimm_t8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: mvni v1.4s, #1, msl #16
+; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t1:
define dso_local void @bic_modimm_t1() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.4s, #1
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t2:
define dso_local void @bic_modimm_t2() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #8
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.4s, #1, lsl #8
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t3:
define dso_local void @bic_modimm_t3() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #16
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.4s, #1, lsl #16
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t4:
define dso_local void @bic_modimm_t4() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #24
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.4s, #1, lsl #24
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t5:
define dso_local void @bic_modimm_t5() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.8h, #1
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: bic_modimm_t6:
define dso_local void @bic_modimm_t6() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1, lsl #8
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: bic_modimm_t6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: bic v0.8h, #1, lsl #8
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t1:
define dso_local void @orr_modimm_t1() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.4s, #1
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t2:
define dso_local void @orr_modimm_t2() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #8
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.4s, #1, lsl #8
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t3:
define dso_local void @orr_modimm_t3() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #16
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.4s, #1, lsl #16
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t4:
define dso_local void @orr_modimm_t4() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #24
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.4s, #1, lsl #24
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t5:
define dso_local void @orr_modimm_t5() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.8h, #1
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void
}
-; CHECK-LABEL: orr_modimm_t6:
define dso_local void @orr_modimm_t6() nounwind {
- ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
- ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1, lsl #8
- ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
+; CHECK-LABEL: orr_modimm_t6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, vec_v8i16
+; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
+; CHECK-NEXT: ld1 { v0.8h }, [x8]
+; CHECK-NEXT: orr v0.8h, #1, lsl #8
+; CHECK-NEXT: st1 { v0.8h }, [x8]
+; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16
@@ -383,448 +512,520 @@ declare i16 @f_v8i16(<8 x i16> %arg)
declare i32 @f_v4i32(<4 x i32> %arg)
declare i64 @f_v2i64(<2 x i64> %arg)
-; CHECK-LABEL: modimm_t1_call:
define dso_local void @modimm_t1_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t1_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 7, i16 0, i16 7, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 6, i32 6>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 21474836485>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 8589934594, i64 8589934594>)
ret void
}
-; CHECK-LABEL: modimm_t2_call:
define dso_local void @modimm_t2_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t2_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8, lsl #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7, lsl #8
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6, lsl #8
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5, lsl #8
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5, lsl #8
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4, lsl #8
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3, lsl #8
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2, lsl #8
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 1792, i16 0, i16 1792, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 1536, i32 1536>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #8
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 5497558140160>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 768, i32 768, i32 768, i32 768>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #8
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 2199023256064, i64 2199023256064>)
ret void
}
-; CHECK-LABEL: modimm_t3_call:
define dso_local void @modimm_t3_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t3_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8, lsl #16
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7, lsl #16
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6, lsl #16
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5, lsl #16
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5, lsl #16
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4, lsl #16
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3, lsl #16
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2, lsl #16
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 0, i16 7, i16 0, i16 7>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 393216, i32 393216>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #16
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 1407374883880960>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 196608, i32 196608, i32 196608, i32 196608>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #16
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 562949953552384, i64 562949953552384>)
ret void
}
-; CHECK-LABEL: modimm_t4_call:
define dso_local void @modimm_t4_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #24
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t4_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8, lsl #24
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7, lsl #24
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6, lsl #24
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5, lsl #24
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5, lsl #24
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4, lsl #24
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3, lsl #24
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2, lsl #24
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #24
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 0, i16 1792, i16 0, i16 1792>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #24
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 100663296, i32 100663296>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #24
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 360287970273525760>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #24
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #24
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #24
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 50331648, i32 50331648, i32 50331648, i32 50331648>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #24
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 144115188109410304, i64 144115188109410304>)
ret void
}
-; CHECK-LABEL: modimm_t5_call:
define dso_local void @modimm_t5_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t5_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.4h, #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.4h, #7
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.4h, #6
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.4h, #5
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.8h, #5
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.8h, #4
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.8h, #3
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.8h, #2
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #7
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 7, i16 7, i16 7, i16 7>)
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #6
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 393222, i32 393222>)
- ; CHECK: movi v{{[0-9]+}}.4h, #5
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 1407396358717445>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #5
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #4
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #3
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 196611, i32 196611, i32 196611, i32 196611>)
- ; CHECK: movi v[[REG:[0-9]+]].8h, #2
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 562958543486978, i64 562958543486978>)
ret void
}
-; CHECK-LABEL: modimm_t6_call:
define dso_local void @modimm_t6_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #8, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t6_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.4h, #8, lsl #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.4h, #7, lsl #8
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.4h, #6, lsl #8
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.4h, #5, lsl #8
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.8h, #5, lsl #8
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.8h, #4, lsl #8
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.8h, #3, lsl #8
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.8h, #2, lsl #8
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8>)
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #7, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 1792, i16 1792, i16 1792, i16 1792>)
- ; CHECK: movi v[[REG1:[0-9]+]].4h, #6, lsl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 100664832, i32 100664832>)
- ; CHECK: movi v{{[0-9]+}}.4h, #5, lsl #8
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 360293467831665920>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #5, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #4, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024>)
- ; CHECK: movi v[[REG1:[0-9]+]].8h, #3, lsl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 50332416, i32 50332416, i32 50332416, i32 50332416>)
- ; CHECK: movi v[[REG:[0-9]+]].8h, #2, lsl #8
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 144117387132666368, i64 144117387132666368>)
ret void
}
-; CHECK-LABEL: modimm_t7_call:
define dso_local void @modimm_t7_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t7_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8, msl #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7, msl #8
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6, msl #8
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5, msl #8
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5, msl #8
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4, msl #8
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3, msl #8
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2, msl #8
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 255, i8 8, i8 0, i8 0, i8 255, i8 8, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, msl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 2047, i16 0, i16 2047, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, msl #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 1791, i32 1791>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5, msl #8
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 6592774800895>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, msl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, msl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, msl #8
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2, msl #8
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 3294239916799, i64 3294239916799>)
ret void
}
-; CHECK-LABEL: modimm_t8_call:
define dso_local void @modimm_t8_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t8_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.2s, #8, msl #16
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.2s, #7, msl #16
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2s, #6, msl #16
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2s, #5, msl #16
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: movi v0.4s, #5, msl #16
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.4s, #4, msl #16
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.4s, #3, msl #16
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: movi v0.4s, #2, msl #16
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 255, i8 255, i8 8, i8 0, i8 255, i8 255, i8 8, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, msl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 65535, i16 7, i16 65535, i16 7>)
- ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, msl #16
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 458751, i32 458751>)
- ; CHECK: movi v{{[0-9]+}}.2s, #5, msl #16
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 1688845565689855>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, msl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, msl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4>)
- ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, msl #16
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 262143, i32 262143, i32 262143, i32 262143>)
- ; CHECK: movi v[[REG:[0-9]+]].4s, #2, msl #16
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 844420635361279, i64 844420635361279>)
ret void
}
-; CHECK-LABEL: modimm_t9_call:
define dso_local void @modimm_t9_call() {
- ; CHECK: movi v[[REG1:[0-9]+]].8b, #8
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t9_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi v0.8b, #8
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi v0.8b, #7
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.8b, #6
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.16b, #5
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.16b, #4
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.16b, #3
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
- ; CHECK: movi v[[REG1:[0-9]+]].8b, #7
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 1799, i16 1799, i16 1799, i16 1799>)
- ; CHECK: movi v[[REG1:[0-9]+]].8b, #6
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 101058054, i32 101058054>)
- ; CHECK: movi v[[REG1:[0-9]+]].16b, #5
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>)
- ; CHECK: movi v[[REG1:[0-9]+]].16b, #4
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>)
- ; CHECK: movi v[[REG1:[0-9]+]].16b, #3
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 50529027, i32 50529027, i32 50529027, i32 50529027>)
ret void
}
-; CHECK-LABEL: modimm_t10_call:
define dso_local void @modimm_t10_call() {
- ; CHECK: movi d[[REG1:[0-9]+]], #0x0000ff000000ff
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t10_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: movi d0, #0x0000ff000000ff
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: movi d0, #0x00ffff0000ffff
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: movi v0.2d, #0xffffff00ffffff
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: movi v0.2d, #0xffffffffffff0000
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: movi v0.2d, #0xffffffff00000000
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>)
- ; CHECK: movi d[[REG1:[0-9]+]], #0x00ffff0000ffff
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 -1, i16 0, i16 -1, i16 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffffffffffffff
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 -1, i32 -1>)
- ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffff00ffffff
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0>)
- ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffffffffff0000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1, i16 -1>)
- ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffffff00000000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 0, i32 -1, i32 0, i32 -1>)
ret void
}
-; CHECK-LABEL: modimm_t11_call:
define dso_local void @modimm_t11_call() {
- ; CHECK: fmov v[[REG1:[0-9]+]].2s, #4.00000000
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
- ; CHECK-NEXT: bl f_v8i8
+; CHECK-LABEL: modimm_t11_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: fmov v0.2s, #4.00000000
+; CHECK-NEXT: rev64 v0.8b, v0.8b
+; CHECK-NEXT: bl f_v8i8
+; CHECK-NEXT: fmov v0.2s, #3.75000000
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: bl f_v4i16
+; CHECK-NEXT: fmov v0.2s, #3.50000000
+; CHECK-NEXT: rev64 v0.2s, v0.2s
+; CHECK-NEXT: bl f_v2i32
+; CHECK-NEXT: fmov v0.2s, #0.39062500
+; CHECK-NEXT: bl f_v1i64
+; CHECK-NEXT: fmov v0.4s, #3.25000000
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: fmov v0.4s, #3.00000000
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: fmov v0.4s, #2.75000000
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: fmov v0.4s, #2.50000000
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v2i64
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 128, i8 64, i8 0, i8 0, i8 128, i8 64>)
- ; CHECK: fmov v[[REG1:[0-9]+]].2s, #3.75000000
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
- ; CHECK-NEXT: bl f_v4i16
call i16 @f_v4i16(<4 x i16> <i16 0, i16 16496, i16 0, i16 16496>)
- ; CHECK: fmov v[[REG1:[0-9]+]].2s, #3.50000000
- ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
- ; CHECK-NEXT: bl f_v2i32
call i32 @f_v2i32(<2 x i32> <i32 1080033280, i32 1080033280>)
- ; CHECK: fmov v{{[0-9]+}}.2s, #0.39062500
- ; CHECK-NEXT: bl f_v1i64
call i64 @f_v1i64(<1 x i64> <i64 4523865826746957824>)
- ; CHECK: fmov v[[REG1:[0-9]+]].4s, #3.25000000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64>)
- ; CHECK: fmov v[[REG1:[0-9]+]].4s, #3.00000000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>)
- ; CHECK: fmov v[[REG1:[0-9]+]].4s, #2.75000000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 1076887552, i32 1076887552, i32 1076887552, i32 1076887552>)
- ; CHECK: fmov v[[REG:[0-9]+]].4s, #2.5000000
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v2i64
call i64 @f_v2i64(<2 x i64> <i64 4620693218757967872, i64 4620693218757967872>)
ret void
}
-; CHECK-LABEL: modimm_t12_call:
define dso_local void @modimm_t12_call() {
- ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.18750000
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v16i8
+; CHECK-LABEL: modimm_t12_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: fmov v0.2d, #0.18750000
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v16i8
+; CHECK-NEXT: fmov v0.2d, #0.17968750
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v8i16
+; CHECK-NEXT: fmov v0.2d, #0.17187500
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: bl f_v4i32
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63>)
- ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.17968750
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v8i16
call i16 @f_v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>)
- ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.17187500
- ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
- ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
- ; CHECK-NEXT: bl f_v4i32
call i32 @f_v4i32(<4 x i32> <i32 0, i32 1069940736, i32 0, i32 1069940736>)
ret void
diff --git a/llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll b/llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
index 55ddaf8b65f1..14f957392b6a 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+lsl-fast | FileCheck %s
%struct.a = type [256 x i16]
@@ -7,10 +8,19 @@
declare void @foo()
define i16 @halfword(%struct.a* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: halfword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldrh [[REG1:w[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #1]
-; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]
-; CHECK: strh [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #1]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: ubfx x21, x1, #9, #8
+; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: ldrh w20, [x0, x21, lsl #1]
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: bl foo
+; CHECK-NEXT: strh w20, [x19, x21, lsl #1]
+; CHECK-NEXT: mov w0, w20
+; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
%shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255
@@ -23,10 +33,19 @@ define i16 @halfword(%struct.a* %ctx, i32 %xor72) nounwind {
define i32 @word(%struct.b* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: word:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldr [[REG1:w[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #2]
-; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]
-; CHECK: str [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: ubfx x21, x1, #9, #8
+; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: ldr w20, [x0, x21, lsl #2]
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: bl foo
+; CHECK-NEXT: str w20, [x19, x21, lsl #2]
+; CHECK-NEXT: mov w0, w20
+; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
%shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255
@@ -39,10 +58,19 @@ define i32 @word(%struct.b* %ctx, i32 %xor72) nounwind {
define i64 @doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
; CHECK-LABEL: doubleword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldr [[REG1:x[0-9]+]], [{{.*}}[[REG2:x[0-9]+]], [[REG]], lsl #3]
-; CHECK: mov [[REG3:x[0-9]+]], [[REG2]]
-; CHECK: str [[REG1]], [{{.*}}[[REG3]], [[REG]], lsl #3]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: ubfx x21, x1, #9, #8
+; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: ldr x20, [x0, x21, lsl #3]
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: bl foo
+; CHECK-NEXT: str x20, [x19, x21, lsl #3]
+; CHECK-NEXT: mov x0, x20
+; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
%shr81 = lshr i32 %xor72, 9
%conv82 = zext i32 %shr81 to i64
%idxprom83 = and i64 %conv82, 255
@@ -55,10 +83,19 @@ define i64 @doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
define i64 @multi_use_non_memory(i64 %a, i64 %b) {
; CHECK-LABEL: multi_use_non_memory:
-; CHECK: lsl [[REG1:x[0-9]+]], x0, #3
-; CHECK-NOT: cmp [[REG1]], x1, lsl # 3
-; CHECK-NEXT: lsl [[REG2:x[0-9]+]], x1, #3
-; CHECK-NEXT: cmp [[REG1]], [[REG2]]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsl x8, x0, #3
+; CHECK-NEXT: lsl x9, x1, #3
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: b.lt .LBB3_2
+; CHECK-NEXT: // %bb.1: // %falsebb
+; CHECK-NEXT: csel x0, x8, x9, gt
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_2: // %truebb
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl foo
entry:
%mul1 = shl i64 %a, 3
%mul2 = shl i64 %b, 3
diff --git a/llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll b/llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
index 6ac60d6fc998..e2e1d33e3964 100644
--- a/llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
+++ b/llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu -o - %s | FileCheck %s
;; Check that the llvm aarch64 backend can handle arrays of
@@ -17,28 +18,31 @@
define [ 0 x double ] @array_0() {
; CHECK-LABEL: array_0:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
ret [ 0 x double ] zeroinitializer
}
define [ 1 x double ] @array_1() {
; CHECK-LABEL: array_1:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: ret
ret [ 1 x double ] zeroinitializer
}
define [ 8 x double ] @array_8() {
; CHECK-LABEL: array_8:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: movi d5, #0000000000000000
-; CHECK-NEXT: movi d6, #0000000000000000
-; CHECK-NEXT: movi d7, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: movi d5, #0000000000000000
+; CHECK-NEXT: movi d6, #0000000000000000
+; CHECK-NEXT: movi d7, #0000000000000000
+; CHECK-NEXT: ret
ret [ 8 x double ] zeroinitializer
}
@@ -46,11 +50,12 @@ define [ 8 x double ] @array_8() {
define [ 9 x double ] @array_9() {
; CHECK-LABEL: array_9:
-; CHECK: movi v0.2d, #0000000000000000
-; CHECK-NEXT: str xzr, [x8, #64]
-; CHECK-NEXT: stp q0, q0, [x8, #32]
-; CHECK-NEXT: stp q0, q0, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: str xzr, [x8, #64]
+; CHECK-NEXT: stp q0, q0, [x8, #32]
+; CHECK-NEXT: stp q0, q0, [x8]
+; CHECK-NEXT: ret
ret [ 9 x double ] zeroinitializer
}
@@ -59,19 +64,22 @@ define [ 9 x double ] @array_9() {
define %T_STRUCT_0M @struct_zero_fields() {
; CHECK-LABEL: struct_zero_fields:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
ret %T_STRUCT_0M zeroinitializer
}
define [ 1 x %T_STRUCT_0M ] @array_of_struct_zero_fields() {
; CHECK-LABEL: array_of_struct_zero_fields:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_0M ] zeroinitializer
}
define [ 2 x %T_STRUCT_0M ] @array_of_struct_zero_fields_in_struct() {
; CHECK-LABEL: array_of_struct_zero_fields_in_struct:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_0M ] zeroinitializer
}
@@ -79,24 +87,27 @@ define [ 2 x %T_STRUCT_0M ] @array_of_struct_zero_fields_in_struct() {
define %T_STRUCT_1M @struct_one_field() {
; CHECK-LABEL: struct_one_field:
-; CHECK: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret %T_STRUCT_1M zeroinitializer
}
define [ 1 x %T_STRUCT_1M ] @array_of_struct_one_field() {
; CHECK-LABEL: array_of_struct_one_field:
-; CHECK: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_1M ] zeroinitializer
}
;; This one will be a reg block
define [ 2 x %T_STRUCT_1M ] @array_of_struct_one_field_2() {
; CHECK-LABEL: array_of_struct_one_field_2:
-; CHECK: w0, wzr
-; CHECK: w1, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_1M ] zeroinitializer
}
@@ -105,27 +116,30 @@ define [ 2 x %T_STRUCT_1M ] @array_of_struct_one_field_2() {
define %T_STRUCT_DIFFM @struct_
diff erent_field_types() {
; CHECK-LABEL: struct_
diff erent_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret %T_STRUCT_DIFFM zeroinitializer
}
define [ 1 x %T_STRUCT_DIFFM ] @array_of_struct_
diff erent_field_types() {
; CHECK-LABEL: array_of_struct_
diff erent_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_DIFFM ] zeroinitializer
}
define [ 2 x %T_STRUCT_DIFFM ] @array_of_struct_
diff erent_field_types_2() {
; CHECK-LABEL: array_of_struct_
diff erent_field_types_2:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: w1, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_DIFFM ] zeroinitializer
}
@@ -135,27 +149,30 @@ define [ 2 x %T_STRUCT_DIFFM ] @array_of_struct_
diff erent_field_types_2() {
;; Here isn't a block as such, we just allocate two consecutive registers
define %T_STRUCT_SAMEM @struct_same_field_types() {
; CHECK-LABEL: struct_same_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: ret
ret %T_STRUCT_SAMEM zeroinitializer
}
define [ 1 x %T_STRUCT_SAMEM ] @array_of_struct_same_field_types() {
; CHECK-LABEL: array_of_struct_same_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_SAMEM ] zeroinitializer
}
define [ 2 x %T_STRUCT_SAMEM ] @array_of_struct_same_field_types_2() {
; CHECK-LABEL: array_of_struct_same_field_types_2:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_SAMEM ] zeroinitializer
}
@@ -164,27 +181,30 @@ define [ 2 x %T_STRUCT_SAMEM ] @array_of_struct_same_field_types_2() {
define %T_STRUCT_SAMEM_INT @struct_same_field_types_int() {
; CHECK-LABEL: struct_same_field_types_int:
-; CHECK: x0, xzr
-; CHECK-NEXT: x1, xzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: ret
ret %T_STRUCT_SAMEM_INT zeroinitializer
}
define [ 1 x %T_STRUCT_SAMEM_INT ] @array_of_struct_same_field_types_int() {
; CHECK-LABEL: array_of_struct_same_field_types_int:
-; CHECK: x0, xzr
-; CHECK-NEXT: x1, xzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_SAMEM_INT ] zeroinitializer
}
define [ 2 x %T_STRUCT_SAMEM_INT ] @array_of_struct_same_field_types_int_2() {
; CHECK-LABEL: array_of_struct_same_field_types_int_2:
-; CHECK: x0, xzr
-; CHECK-NEXT: x1, xzr
-; CHECK-NEXT: x2, xzr
-; CHECK-NEXT: x3, xzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: mov x2, xzr
+; CHECK-NEXT: mov x3, xzr
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_SAMEM_INT ] zeroinitializer
}
@@ -193,15 +213,16 @@ define [ 2 x %T_STRUCT_SAMEM_INT ] @array_of_struct_same_field_types_int_2() {
define [ 4 x %T_STRUCT_SAMEM ] @array_of_struct_8_fields() {
; CHECK-LABEL: array_of_struct_8_fields:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: movi d5, #0000000000000000
-; CHECK-NEXT: movi d6, #0000000000000000
-; CHECK-NEXT: movi d7, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: movi d5, #0000000000000000
+; CHECK-NEXT: movi d6, #0000000000000000
+; CHECK-NEXT: movi d7, #0000000000000000
+; CHECK-NEXT: ret
ret [ 4 x %T_STRUCT_SAMEM ] zeroinitializer
}
@@ -209,11 +230,12 @@ define [ 4 x %T_STRUCT_SAMEM ] @array_of_struct_8_fields() {
define [ 5 x %T_STRUCT_SAMEM ] @array_of_struct_in_memory() {
; CHECK-LABEL: array_of_struct_in_memory:
-; CHECK: movi v0.2d, #0000000000000000
-; CHECK-NEXT: stp q0, q0, [x8, #48]
-; CHECK-NEXT: stp q0, q0, [x8, #16]
-; CHECK-NEXT: str q0, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: stp q0, q0, [x8, #48]
+; CHECK-NEXT: stp q0, q0, [x8, #16]
+; CHECK-NEXT: str q0, [x8]
+; CHECK-NEXT: ret
ret [ 5 x %T_STRUCT_SAMEM ] zeroinitializer
}
@@ -222,27 +244,30 @@ define [ 5 x %T_STRUCT_SAMEM ] @array_of_struct_in_memory() {
define %T_STRUCT_ARRAYM @struct_array_field() {
; CHECK-LABEL: struct_array_field:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: ret
ret %T_STRUCT_ARRAYM zeroinitializer
}
define [ 1 x %T_STRUCT_ARRAYM ] @array_of_struct_array_field() {
; CHECK-LABEL: array_of_struct_array_field:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: ret
ret [ 1 x %T_STRUCT_ARRAYM ] zeroinitializer
}
define [ 2 x %T_STRUCT_ARRAYM ] @array_of_struct_array_field_2() {
; CHECK-LABEL: array_of_struct_array_field_2:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: ret
ret [ 2 x %T_STRUCT_ARRAYM ] zeroinitializer
}
@@ -255,35 +280,38 @@ define [ 2 x %T_STRUCT_ARRAYM ] @array_of_struct_array_field_2() {
define %T_NESTED_STRUCT_DIFFM @struct_nested_
diff erent_field_types() {
; CHECK-LABEL: struct_nested_
diff erent_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK: movi d1, #0000000000000000
-; CHECK: movi d2, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret %T_NESTED_STRUCT_DIFFM zeroinitializer
}
define [ 1 x %T_NESTED_STRUCT_DIFFM ] @array_of_struct_nested_
diff erent_field_types() {
; CHECK-LABEL: array_of_struct_nested_
diff erent_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK: movi d1, #0000000000000000
-; CHECK: movi d2, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
ret [ 1 x %T_NESTED_STRUCT_DIFFM ] zeroinitializer
}
define [ 2 x %T_NESTED_STRUCT_DIFFM ] @array_of_struct_nested_
diff erent_field_types_2() {
; CHECK-LABEL: array_of_struct_nested_
diff erent_field_types_2:
-; CHECK: movi d0, #0000000000000000
-; CHECK: movi d1, #0000000000000000
-; CHECK: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: movi d5, #0000000000000000
-; CHECK-NEXT: w0, wzr
-; CHECK-NEXT: w1, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: movi d5, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: ret
ret [ 2 x %T_NESTED_STRUCT_DIFFM ] zeroinitializer
}
@@ -295,34 +323,37 @@ define [ 2 x %T_NESTED_STRUCT_DIFFM ] @array_of_struct_nested_
diff erent_field_ty
define %T_NESTED_STRUCT_SAMEM @struct_nested_same_field_types() {
; CHECK-LABEL: struct_nested_same_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: ret
ret %T_NESTED_STRUCT_SAMEM zeroinitializer
}
define [ 1 x %T_NESTED_STRUCT_SAMEM ] @array_of_struct_nested_same_field_types() {
; CHECK-LABEL: array_of_struct_nested_same_field_types:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: ret
ret [ 1 x %T_NESTED_STRUCT_SAMEM ] zeroinitializer
}
;; 2 x (1 + (2 x 2)) = 10 so this is returned in memory
define [ 2 x %T_NESTED_STRUCT_SAMEM ] @array_of_struct_nested_same_field_types_2() {
; CHECK-LABEL: array_of_struct_nested_same_field_types_2:
-; CHECK: movi v0.2d, #0000000000000000
-; CHECK-NEXT: stp q0, q0, [x8, #48]
-; CHECK-NEXT: stp q0, q0, [x8, #16]
-; CHECK-NEXT: str q0, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: stp q0, q0, [x8, #48]
+; CHECK-NEXT: stp q0, q0, [x8, #16]
+; CHECK-NEXT: str q0, [x8]
+; CHECK-NEXT: ret
ret [ 2 x %T_NESTED_STRUCT_SAMEM ] zeroinitializer
}
@@ -332,13 +363,14 @@ define [ 2 x %T_NESTED_STRUCT_SAMEM ] @array_of_struct_nested_same_field_types_2
define %T_IN_BLOCK @return_in_block() {
; CHECK-LABEL: return_in_block:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: movi d2, #0000000000000000
-; CHECK-NEXT: movi d3, #0000000000000000
-; CHECK-NEXT: movi d4, #0000000000000000
-; CHECK-NEXT: movi d5, #0000000000000000
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: movi d2, #0000000000000000
+; CHECK-NEXT: movi d3, #0000000000000000
+; CHECK-NEXT: movi d4, #0000000000000000
+; CHECK-NEXT: movi d5, #0000000000000000
+; CHECK-NEXT: ret
ret %T_IN_BLOCK zeroinitializer
}
@@ -346,14 +378,18 @@ define %T_IN_BLOCK @return_in_block() {
define void @caller_in_block() {
; CHECK-LABEL: caller_in_block:
-; CHECK: bl return_in_block
-; CHECK-NEXT: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: stp d0, d1, [x8]
-; CHECK-NEXT: stp d2, d3, [x8, #16]
-; CHECK-NEXT: stp d4, d5, [x8, #32]
-; CHECK-NEXT: ldr x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl return_in_block
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: stp d0, d1, [x8]
+; CHECK-NEXT: stp d2, d3, [x8, #16]
+; CHECK-NEXT: stp d4, d5, [x8, #32]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%1 = call %T_IN_BLOCK @return_in_block()
store %T_IN_BLOCK %1, %T_IN_BLOCK* @in_block_store
ret void
@@ -361,24 +397,31 @@ define void @caller_in_block() {
define void @callee_in_block(%T_IN_BLOCK %a) {
; CHECK-LABEL: callee_in_block:
-; CHECK: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: stp d4, d5, [x8, #32]
-; CHECK-NEXT: stp d2, d3, [x8, #16]
-; CHECK-NEXT: stp d0, d1, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: stp d4, d5, [x8, #32]
+; CHECK-NEXT: stp d2, d3, [x8, #16]
+; CHECK-NEXT: stp d0, d1, [x8]
+; CHECK-NEXT: ret
store %T_IN_BLOCK %a, %T_IN_BLOCK* @in_block_store
ret void
}
define void @argument_in_block() {
; CHECK-LABEL: argument_in_block:
-; CHECK: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: ldp d4, d5, [x8, #32]
-; CHECK-NEXT: ldp d2, d3, [x8, #16]
-; CHECK-NEXT: ldp d0, d1, [x8]
-; CHECK-NEXT: bl callee_in_block
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: ldp d4, d5, [x8, #32]
+; CHECK-NEXT: ldp d2, d3, [x8, #16]
+; CHECK-NEXT: ldp d0, d1, [x8]
+; CHECK-NEXT: bl callee_in_block
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%1 = load %T_IN_BLOCK, %T_IN_BLOCK* @in_block_store
call void @callee_in_block(%T_IN_BLOCK %1)
ret void
@@ -388,11 +431,12 @@ define void @argument_in_block() {
define %T_IN_MEMORY @return_in_memory() {
; CHECK-LABEL: return_in_memory:
-; CHECK: movi v0.2d, #0000000000000000
-; CHECK-NEXT: str xzr, [x8, #64]
-; CHECK-NEXT: stp q0, q0, [x8, #32]
-; CHECK-NEXT: stp q0, q0, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: str xzr, [x8, #64]
+; CHECK-NEXT: stp q0, q0, [x8, #32]
+; CHECK-NEXT: stp q0, q0, [x8]
+; CHECK-NEXT: ret
ret %T_IN_MEMORY zeroinitializer
}
@@ -400,21 +444,26 @@ define %T_IN_MEMORY @return_in_memory() {
define void @caller_in_memory() {
; CHECK-LABEL: caller_in_memory:
-; CHECK: add x8, sp, #8
-; CHECK-NEXT: bl return_in_memory
-; CHECK-NEXT: ldr d0, [sp, #72]
-; CHECK-NEXT: ldur q1, [sp, #24]
-; CHECK-NEXT: ldur q2, [sp, #8]
-; CHECK-NEXT: ldur q3, [sp, #56]
-; CHECK-NEXT: ldur q4, [sp, #40]
-; CHECK-NEXT: ldr x30, [sp, #80]
-; CHECK-NEXT: adrp x8, in_memory_store
-; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
-; CHECK-NEXT: stp q2, q1, [x8]
-; CHECK-NEXT: stp q4, q3, [x8, #32]
-; CHECK-NEXT: str d0, [x8, #64]
-; CHECK-NEXT: add sp, sp, #96
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #96
+; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 96
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: add x8, sp, #8
+; CHECK-NEXT: bl return_in_memory
+; CHECK-NEXT: ldr d0, [sp, #72]
+; CHECK-NEXT: ldur q1, [sp, #24]
+; CHECK-NEXT: ldur q2, [sp, #8]
+; CHECK-NEXT: ldur q3, [sp, #56]
+; CHECK-NEXT: ldur q4, [sp, #40]
+; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
+; CHECK-NEXT: adrp x8, in_memory_store
+; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
+; CHECK-NEXT: stp q2, q1, [x8]
+; CHECK-NEXT: stp q4, q3, [x8, #32]
+; CHECK-NEXT: str d0, [x8, #64]
+; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: ret
%1 = call %T_IN_MEMORY @return_in_memory()
store %T_IN_MEMORY %1, %T_IN_MEMORY* @in_memory_store
ret void
@@ -422,30 +471,39 @@ define void @caller_in_memory() {
define void @callee_in_memory(%T_IN_MEMORY %a) {
; CHECK-LABEL: callee_in_memory:
-; CHECK: ldp q0, q1, [sp, #32]
-; CHECK-NEXT: ldr d2, [sp, #64]
-; CHECK-NEXT: ldp q3, q4, [sp]
-; CHECK-NEXT: adrp x8, in_memory_store
-; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
-; CHECK-NEXT: str d2, [x8, #64]
-; CHECK-NEXT: stp q0, q1, [x8, #32]
-; CHECK-NEXT: stp q3, q4, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [sp, #32]
+; CHECK-NEXT: ldr d2, [sp, #64]
+; CHECK-NEXT: ldp q3, q4, [sp]
+; CHECK-NEXT: adrp x8, in_memory_store
+; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
+; CHECK-NEXT: str d2, [x8, #64]
+; CHECK-NEXT: stp q0, q1, [x8, #32]
+; CHECK-NEXT: stp q3, q4, [x8]
+; CHECK-NEXT: ret
store %T_IN_MEMORY %a, %T_IN_MEMORY* @in_memory_store
ret void
}
define void @argument_in_memory() {
; CHECK-LABEL: argument_in_memory:
-; CHECK: adrp x8, in_memory_store
-; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
-; CHECK-NEXT: ldp q0, q1, [x8]
-; CHECK-NEXT: ldp q2, q3, [x8, #32]
-; CHECK-NEXT: ldr d4, [x8, #64]
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: str d4, [sp, #64]
-; CHECK-NEXT: bl callee_in_memory
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #96
+; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 96
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: adrp x8, in_memory_store
+; CHECK-NEXT: add x8, x8, :lo12:in_memory_store
+; CHECK-NEXT: ldp q0, q1, [x8]
+; CHECK-NEXT: ldp q2, q3, [x8, #32]
+; CHECK-NEXT: ldr d4, [x8, #64]
+; CHECK-NEXT: stp q0, q1, [sp]
+; CHECK-NEXT: stp q2, q3, [sp, #32]
+; CHECK-NEXT: str d4, [sp, #64]
+; CHECK-NEXT: bl callee_in_memory
+; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: ret
%1 = load %T_IN_MEMORY, %T_IN_MEMORY* @in_memory_store
call void @callee_in_memory(%T_IN_MEMORY %1)
ret void
@@ -455,11 +513,12 @@ define void @argument_in_memory() {
define %T_NO_BLOCK @return_no_block() {
; CHECK-LABEL: return_no_block:
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: mov w0, wzr
-; CHECK-NEXT: mov w1, wzr
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: ret
ret %T_NO_BLOCK zeroinitializer
}
@@ -467,15 +526,19 @@ define %T_NO_BLOCK @return_no_block() {
define void @caller_no_block() {
; CHECK-LABEL: caller_no_block:
-; CHECK: bl return_no_block
-; CHECK-NEXT: adrp x8, no_block_store
-; CHECK-NEXT: add x8, x8, :lo12:no_block_store
-; CHECK-NEXT: str d0, [x8]
-; CHECK-NEXT: str w0, [x8, #8]
-; CHECK-NEXT: str d1, [x8, #16]
-; CHECK-NEXT: str w1, [x8, #24]
-; CHECK-NEXT: ldr x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl return_no_block
+; CHECK-NEXT: adrp x8, no_block_store
+; CHECK-NEXT: add x8, x8, :lo12:no_block_store
+; CHECK-NEXT: str d0, [x8]
+; CHECK-NEXT: str w0, [x8, #8]
+; CHECK-NEXT: str d1, [x8, #16]
+; CHECK-NEXT: str w1, [x8, #24]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%1 = call %T_NO_BLOCK @return_no_block()
store %T_NO_BLOCK %1, %T_NO_BLOCK* @no_block_store
ret void
@@ -483,28 +546,33 @@ define void @caller_no_block() {
define void @callee_no_block(%T_NO_BLOCK %a) {
; CHECK-LABEL: callee_no_block:
-; CHECK: adrp x8, no_block_store
-; CHECK-NEXT: add x8, x8, :lo12:no_block_store
-; CHECK-NEXT: str w1, [x8, #24]
-; CHECK-NEXT: str d1, [x8, #16]
-; CHECK-NEXT: str w0, [x8, #8]
-; CHECK-NEXT: str d0, [x8]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, no_block_store
+; CHECK-NEXT: add x8, x8, :lo12:no_block_store
+; CHECK-NEXT: str w1, [x8, #24]
+; CHECK-NEXT: str d1, [x8, #16]
+; CHECK-NEXT: str w0, [x8, #8]
+; CHECK-NEXT: str d0, [x8]
+; CHECK-NEXT: ret
store %T_NO_BLOCK %a, %T_NO_BLOCK* @no_block_store
ret void
}
define void @argument_no_block() {
; CHECK-LABEL: argument_no_block:
-; CHECK: adrp x8, no_block_store
-; CHECK-NEXT: add x8, x8, :lo12:no_block_store
-; CHECK-NEXT: ldr w1, [x8, #24]
-; CHECK-NEXT: ldr d1, [x8, #16]
-; CHECK-NEXT: ldr w0, [x8, #8]
-; CHECK-NEXT: ldr d0, [x8]
-; CHECK-NEXT: bl callee_no_block
-; CHECK-NEXT: ldr x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: adrp x8, no_block_store
+; CHECK-NEXT: add x8, x8, :lo12:no_block_store
+; CHECK-NEXT: ldr w1, [x8, #24]
+; CHECK-NEXT: ldr d1, [x8, #16]
+; CHECK-NEXT: ldr w0, [x8, #8]
+; CHECK-NEXT: ldr d0, [x8]
+; CHECK-NEXT: bl callee_no_block
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%1 = load %T_NO_BLOCK, %T_NO_BLOCK* @no_block_store
call void @callee_no_block(%T_NO_BLOCK %1)
ret void
diff --git a/llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll b/llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
index 8860ffa2962d..cfd3d6ad7bd8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
@@ -15,8 +15,10 @@ entry:
; strict-alignment is turned on.
define void @t1(i8* align 8 %out, i8* align 8 %in) {
; CHECK-LABEL: t1:
-; CHECK: ldp x{{[0-9]+}}, x{{[0-9]+}}, [x1]
-; CHECK-NEXT: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0]
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: ldp x9, x8, [x1]
+; CHECK-NEXT: stp x9, x8, [x0]
+; CHECK-NEXT: ret
entry:
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %out, i8* align 8 %in, i64 16, i1 false)
ret void
@@ -26,14 +28,16 @@ entry:
; loads and stores if strict-alignment is turned on.
define void @t2(i8* %out, i8* %in) {
; CHECK-LABEL: t2:
-; CHECK: ldrb w{{[0-9]+}}, [x1, #3]
-; CHECK-NEXT: ldrb w{{[0-9]+}}, [x1, #2]
-; CHECK-NEXT: ldrb w{{[0-9]+}}, [x1, #1]
-; CHECK-NEXT: ldrb w{{[0-9]+}}, [x1]
-; CHECK-NEXT: strb w{{[0-9]+}}, [x0, #3]
-; CHECK-NEXT: strb w{{[0-9]+}}, [x0, #2]
-; CHECK-NEXT: strb w{{[0-9]+}}, [x0, #1]
-; CHECK-NEXT: strb w{{[0-9]+}}, [x0]
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: ldrb w8, [x1, #3]
+; CHECK-NEXT: ldrb w9, [x1, #2]
+; CHECK-NEXT: ldrb w10, [x1, #1]
+; CHECK-NEXT: ldrb w11, [x1]
+; CHECK-NEXT: strb w8, [x0, #3]
+; CHECK-NEXT: strb w9, [x0, #2]
+; CHECK-NEXT: strb w10, [x0, #1]
+; CHECK-NEXT: strb w11, [x0]
+; CHECK-NEXT: ret
entry:
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 4, i1 false)
ret void
diff --git a/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll b/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
index 12eefa0ffe36..7e1ea72b08fe 100644
--- a/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
+++ b/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
@@ -1,53 +1,106 @@
-; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECKN
-; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu -mattr=strict-align | FileCheck %s --check-prefixes=CHECK,CHECKS
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECKN
+; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu -mattr=strict-align | FileCheck %s --check-prefix=CHECKS
declare i32 @bcmp(i8*, i8*, i64) nounwind readonly
declare i32 @memcmp(i8*, i8*, i64) nounwind readonly
define i1 @test_b2(i8* %s1, i8* %s2) {
+; CHECKN-LABEL: test_b2:
+; CHECKN: // %bb.0: // %entry
+; CHECKN-NEXT: ldr x8, [x0]
+; CHECKN-NEXT: ldr x9, [x1]
+; CHECKN-NEXT: ldur x10, [x0, #7]
+; CHECKN-NEXT: ldur x11, [x1, #7]
+; CHECKN-NEXT: eor x8, x8, x9
+; CHECKN-NEXT: eor x9, x10, x11
+; CHECKN-NEXT: orr x8, x8, x9
+; CHECKN-NEXT: cmp x8, #0
+; CHECKN-NEXT: cset w0, eq
+; CHECKN-NEXT: ret
+;
+; CHECKS-LABEL: test_b2:
+; CHECKS: // %bb.0: // %entry
+; CHECKS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECKS-NEXT: .cfi_def_cfa_offset 16
+; CHECKS-NEXT: .cfi_offset w30, -16
+; CHECKS-NEXT: mov w2, #15
+; CHECKS-NEXT: bl bcmp
+; CHECKS-NEXT: cmp w0, #0
+; CHECKS-NEXT: cset w0, eq
+; CHECKS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECKS-NEXT: ret
entry:
%bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
%ret = icmp eq i32 %bcmp, 0
ret i1 %ret
-
-; CHECK-LABEL: test_b2:
-; CHECKN-NOT: bl bcmp
-; CHECKN: ldr x
-; CHECKN-NEXT: ldr x
-; CHECKN-NEXT: ldur x
-; CHECKN-NEXT: ldur x
-; CHECKS: bl bcmp
}
+; TODO: Four loads should be within the limit, but the heuristic isn't implemented.
define i1 @test_b2_align8(i8* align 8 %s1, i8* align 8 %s2) {
+; CHECKN-LABEL: test_b2_align8:
+; CHECKN: // %bb.0: // %entry
+; CHECKN-NEXT: ldr x8, [x0]
+; CHECKN-NEXT: ldr x9, [x1]
+; CHECKN-NEXT: ldur x10, [x0, #7]
+; CHECKN-NEXT: ldur x11, [x1, #7]
+; CHECKN-NEXT: eor x8, x8, x9
+; CHECKN-NEXT: eor x9, x10, x11
+; CHECKN-NEXT: orr x8, x8, x9
+; CHECKN-NEXT: cmp x8, #0
+; CHECKN-NEXT: cset w0, eq
+; CHECKN-NEXT: ret
+;
+; CHECKS-LABEL: test_b2_align8:
+; CHECKS: // %bb.0: // %entry
+; CHECKS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECKS-NEXT: .cfi_def_cfa_offset 16
+; CHECKS-NEXT: .cfi_offset w30, -16
+; CHECKS-NEXT: mov w2, #15
+; CHECKS-NEXT: bl bcmp
+; CHECKS-NEXT: cmp w0, #0
+; CHECKS-NEXT: cset w0, eq
+; CHECKS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECKS-NEXT: ret
entry:
%bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
%ret = icmp eq i32 %bcmp, 0
ret i1 %ret
-
-; CHECK-LABEL: test_b2_align8:
-; CHECKN-NOT: bl bcmp
-; CHECKN: ldr x
-; CHECKN-NEXT: ldr x
-; CHECKN-NEXT: ldur x
-; CHECKN-NEXT: ldur x
-; TODO: Four loads should be within the limit, but the heuristic isn't implemented.
-; CHECKS: bl bcmp
}
define i1 @test_bs(i8* %s1, i8* %s2) optsize {
+; CHECKN-LABEL: test_bs:
+; CHECKN: // %bb.0: // %entry
+; CHECKN-NEXT: ldp x8, x9, [x0]
+; CHECKN-NEXT: ldp x10, x11, [x1]
+; CHECKN-NEXT: ldr x12, [x0, #16]
+; CHECKN-NEXT: ldr x13, [x1, #16]
+; CHECKN-NEXT: ldur x14, [x0, #23]
+; CHECKN-NEXT: ldur x15, [x1, #23]
+; CHECKN-NEXT: eor x8, x8, x10
+; CHECKN-NEXT: eor x9, x9, x11
+; CHECKN-NEXT: eor x10, x12, x13
+; CHECKN-NEXT: eor x11, x14, x15
+; CHECKN-NEXT: orr x8, x8, x9
+; CHECKN-NEXT: orr x9, x10, x11
+; CHECKN-NEXT: orr x8, x8, x9
+; CHECKN-NEXT: cmp x8, #0
+; CHECKN-NEXT: cset w0, eq
+; CHECKN-NEXT: ret
+;
+; CHECKS-LABEL: test_bs:
+; CHECKS: // %bb.0: // %entry
+; CHECKS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECKS-NEXT: .cfi_def_cfa_offset 16
+; CHECKS-NEXT: .cfi_offset w30, -16
+; CHECKS-NEXT: mov w2, #31
+; CHECKS-NEXT: bl memcmp
+; CHECKS-NEXT: cmp w0, #0
+; CHECKS-NEXT: cset w0, eq
+; CHECKS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECKS-NEXT: ret
entry:
%memcmp = call i32 @memcmp(i8* %s1, i8* %s2, i64 31)
%ret = icmp eq i32 %memcmp, 0
ret i1 %ret
-
-; CHECK-LABEL: test_bs:
-; CHECKN-NOT: bl memcmp
-; CHECKN: ldp x
-; CHECKN-NEXT: ldp x
-; CHECKN-NEXT: ldr x
-; CHECKN-NEXT: ldr x
-; CHECKN-NEXT: ldur x
-; CHECKN-NEXT: ldur x
-; CHECKS: bl memcmp
}
diff --git a/llvm/test/CodeGen/AArch64/build-one-lane.ll b/llvm/test/CodeGen/AArch64/build-one-lane.ll
index 78dfaa9d1769..f991f8bc4ca5 100644
--- a/llvm/test/CodeGen/AArch64/build-one-lane.ll
+++ b/llvm/test/CodeGen/AArch64/build-one-lane.ll
@@ -1,283 +1,332 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
; Check that building up a vector w/ only one non-zero lane initializes
; efficiently.
define <8 x i8> @v8i8z(i8 %t, i8 %s) nounwind {
+; CHECK-LABEL: v8i8z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov v0.b[7], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef>, i8 %s, i32 7
ret <8 x i8> %v
-
-; CHECK-LABEL: v8i8z
-; CHECK: movi d[[R:[0-9]+]], #0
-; CHECK: mov v[[R]].b[7], w{{[0-9]+}}
}
define <16 x i8> @v16i8z(i8 %t, i8 %s) nounwind {
+; CHECK-LABEL: v16i8z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: mov v0.b[15], w1
+; CHECK-NEXT: ret
%v = insertelement <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef>, i8 %s, i32 15
ret <16 x i8> %v
-
-; CHECK-LABEL: v16i8z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].b[15], w{{[0-9]+}}
}
define <4 x i16> @v4i16z(i16 %t, i16 %s) nounwind {
+; CHECK-LABEL: v4i16z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov v0.h[3], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 undef>, i16 %s, i32 3
ret <4 x i16> %v
-
-; CHECK-LABEL: v4i16z:
-; CHECK: movi d[[R:[0-9]+]], #0
-; CHECK: mov v[[R]].h[3], w{{[0-9]+}}
}
define <8 x i16> @v8i16z(i16 %t, i16 %s) nounwind {
+; CHECK-LABEL: v8i16z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: mov v0.h[7], w1
+; CHECK-NEXT: ret
%v = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef>, i16 %s, i32 7
ret <8 x i16> %v
-
-; CHECK-LABEL: v8i16z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].h[7], w{{[0-9]+}}
}
define <2 x i32> @v2i32z(i32 %t, i32 %s) nounwind {
+; CHECK-LABEL: v2i32z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov v0.s[1], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <2 x i32> <i32 0, i32 undef>, i32 %s, i32 1
ret <2 x i32> %v
-
-; CHECK-LABEL: v2i32z:
-; CHECK: movi d[[R:[0-9]+]], #0
-; CHECK: mov v[[R]].s[1], w{{[0-9]+}}
}
define <4 x i32> @v4i32z(i32 %t, i32 %s) nounwind {
+; CHECK-LABEL: v4i32z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: mov v0.s[3], w1
+; CHECK-NEXT: ret
%v = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, i32 %s, i32 3
ret <4 x i32> %v
-
-; CHECK-LABEL: v4i32z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].s[3], w{{[0-9]+}}
}
define <2 x i64> @v2i64z(i64 %t, i64 %s) nounwind {
+; CHECK-LABEL: v2i64z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: mov v0.d[1], x1
+; CHECK-NEXT: ret
%v = insertelement <2 x i64> <i64 0, i64 undef>, i64 %s, i32 1
ret <2 x i64> %v
-
-; CHECK-LABEL: v2i64z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].d[1], x{{[0-9]+}}
}
define <2 x float> @v2f32z(float %t, float %s) nounwind {
+; CHECK-LABEL: v2f32z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <2 x float> <float 0.0, float undef>, float %s, i32 1
ret <2 x float> %v
-
-; CHECK-LABEL: v2f32z:
-; CHECK: movi d[[R:[0-9]+]], #0
-; CHECK: mov v[[R]].s[1], v{{[0-9]+}}.s[0]
}
define <4 x float> @v4f32z(float %t, float %s) nounwind {
+; CHECK-LABEL: v4f32z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: ret
%v = insertelement <4 x float> <float 0.0, float 0.0, float 0.0, float undef>, float %s, i32 3
ret <4 x float> %v
-
-; CHECK-LABEL: v4f32z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].s[3], v{{[0-9]+}}.s[0]
}
define <2 x double> @v2f64z(double %t, double %s) nounwind {
+; CHECK-LABEL: v2f64z:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%v = insertelement <2 x double> <double 0.0, double undef>, double %s, i32 1
ret <2 x double> %v
-
-; CHECK-LABEL: v2f64z:
-; CHECK: movi v[[R:[0-9]+]].2d, #0
-; CHECK: mov v[[R]].d[1], v{{[0-9]+}}.d[0]
}
; Check that building up a vector w/ only one non-ones lane initializes
; efficiently.
define <8 x i8> @v8i8m(i8 %t, i8 %s) nounwind {
+; CHECK-LABEL: v8i8m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.b[7], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 undef>, i8 %s, i32 7
ret <8 x i8> %v
-
-; CHECK-LABEL: v8i8m
-; CHECK: movi d{{[0-9]+}}, #0xffffffffffffffff
-; CHECK: mov v[[R]].b[7], w{{[0-9]+}}
}
define <16 x i8> @v16i8m(i8 %t, i8 %s) nounwind {
+; CHECK-LABEL: v16i8m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.b[15], w1
+; CHECK-NEXT: ret
%v = insertelement <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 undef>, i8 %s, i32 15
ret <16 x i8> %v
-
-; CHECK-LABEL: v16i8m
-; CHECK: movi v[[R:[0-9]+]].2d, #0xffffffffffffffff
-; CHECK: mov v[[R]].b[15], w{{[0-9]+}}
}
define <4 x i16> @v4i16m(i16 %t, i16 %s) nounwind {
+; CHECK-LABEL: v4i16m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.h[3], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <4 x i16> <i16 -1, i16 -1, i16 -1, i16 undef>, i16 %s, i32 3
ret <4 x i16> %v
-
-; CHECK-LABEL: v4i16m
-; CHECK: movi d{{[0-9]+}}, #0xffffffffffffffff
-; CHECK: mov v[[R]].h[3], w{{[0-9]+}}
}
define <8 x i16> @v8i16m(i16 %t, i16 %s) nounwind {
+; CHECK-LABEL: v8i16m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.h[7], w1
+; CHECK-NEXT: ret
%v = insertelement <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 undef>, i16 %s, i32 7
ret <8 x i16> %v
-
-; CHECK-LABEL: v8i16m
-; CHECK: movi v[[R:[0-9]+]].2d, #0xffffffffffffffff
-; CHECK: mov v[[R]].h[7], w{{[0-9]+}}
}
define <2 x i32> @v2i32m(i32 %t, i32 %s) nounwind {
+; CHECK-LABEL: v2i32m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.s[1], w1
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%v = insertelement <2 x i32> <i32 -1, i32 undef>, i32 %s, i32 1
ret <2 x i32> %v
-
-; CHECK-LABEL: v2i32m
-; CHECK: movi d{{[0-9]+}}, #0xffffffffffffffff
-; CHECK: mov v[[R]].s[1], w{{[0-9]+}}
}
define <4 x i32> @v4i32m(i32 %t, i32 %s) nounwind {
+; CHECK-LABEL: v4i32m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.s[3], w1
+; CHECK-NEXT: ret
%v = insertelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 undef>, i32 %s, i32 3
ret <4 x i32> %v
-
-; CHECK-LABEL: v4i32m
-; CHECK: movi v[[R:[0-9]+]].2d, #0xffffffffffffffff
-; CHECK: mov v[[R]].s[3], w{{[0-9]+}}
}
define <2 x i64> @v2i64m(i64 %t, i64 %s) nounwind {
+; CHECK-LABEL: v2i64m:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-NEXT: mov v0.d[1], x1
+; CHECK-NEXT: ret
%v = insertelement <2 x i64> <i64 -1, i64 undef>, i64 %s, i32 1
ret <2 x i64> %v
-
-; CHECK-LABEL: v2i64m
-; CHECK: movi v[[R:[0-9]+]].2d, #0xffffffffffffffff
-; CHECK: mov v[[R]].d[1], x{{[0-9]+}}
}
; Check that building up a vector w/ some constants initializes efficiently.
define void @v8i8st(<8 x i8>* %p, i8 %s) nounwind {
+; CHECK-LABEL: v8i8st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.8b, #1
+; CHECK-NEXT: mov v0.b[7], w1
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 undef>, i8 %s, i32 7
store <8 x i8> %v, <8 x i8>* %p, align 8
ret void
-
-; CHECK-LABEL: v8i8st:
-; CHECK: movi v[[R:[0-9]+]].8b, #1
-; CHECK: mov v[[R]].b[7], w{{[0-9]+}}
-; CHECK: str d[[R]], [x{{[0-9]+}}]
}
define void @v16i8st(<16 x i8>* %p, i8 %s) nounwind {
+; CHECK-LABEL: v16i8st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.16b, #128
+; CHECK-NEXT: mov v0.b[15], w1
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 undef>, i8 %s, i32 15
store <16 x i8> %v, <16 x i8>* %p, align 16
ret void
-
-; CHECK-LABEL: v16i8st:
-; CHECK: movi v[[R:[0-9]+]].16b, #128
-; CHECK: mov v[[R]].b[15], w{{[0-9]+}}
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
define void @v4i16st(<4 x i16>* %p, i16 %s) nounwind {
+; CHECK-LABEL: v4i16st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.4h, #85, lsl #8
+; CHECK-NEXT: mov v0.h[3], w1
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <4 x i16> <i16 21760, i16 21760, i16 21760, i16 undef>, i16 %s, i32 3
store <4 x i16> %v, <4 x i16>* %p, align 8
ret void
-
-; CHECK-LABEL: v4i16st:
-; CHECK: movi v[[R:[0-9]+]].4h, #85, lsl #8
-; CHECK: mov v[[R]].h[3], w{{[0-9]+}}
-; CHECK: str d[[R]], [x{{[0-9]+}}]
}
define void @v8i16st(<8 x i16>* %p, i16 %s) nounwind {
+; CHECK-LABEL: v8i16st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mvni v0.8h, #85, lsl #8
+; CHECK-NEXT: mov v0.h[7], w1
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <8 x i16> <i16 -21761, i16 -21761, i16 -21761, i16 -21761, i16 -21761, i16 -21761, i16 -21761, i16 undef>, i16 %s, i32 7
store <8 x i16> %v, <8 x i16>* %p, align 16
ret void
-
-; CHECK-LABEL: v8i16st:
-; CHECK: mvni v[[R:[0-9]+]].8h, #85, lsl #8
-; CHECK: mov v[[R]].h[7], w{{[0-9]+}}
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
define void @v2i32st(<2 x i32>* %p, i32 %s) nounwind {
+; CHECK-LABEL: v2i32st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2s, #15, lsl #16
+; CHECK-NEXT: mov v0.s[1], w1
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <2 x i32> <i32 983040, i32 undef>, i32 %s, i32 1
store <2 x i32> %v, <2 x i32>* %p, align 8
ret void
-
-; CHECK-LABEL: v2i32st:
-; CHECK: movi v[[R:[0-9]+]].2s, #15, lsl #16
-; CHECK: mov v[[R]].s[1], w{{[0-9]+}}
-; CHECK: str d[[R]], [x{{[0-9]+}}]
}
define void @v4i32st(<4 x i32>* %p, i32 %s) nounwind {
+; CHECK-LABEL: v4i32st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.4s, #248, msl #16
+; CHECK-NEXT: mov v0.s[3], w1
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <4 x i32> <i32 16318463, i32 16318463, i32 16318463, i32 undef>, i32 %s, i32 3
store <4 x i32> %v, <4 x i32>* %p, align 16
ret void
-
-; CHECK-LABEL: v4i32st:
-; CHECK: movi v[[R:[0-9]+]].4s, #248, msl #16
-; CHECK: mov v[[R]].s[3], w{{[0-9]+}}
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
define void @v2i64st(<2 x i64>* %p, i64 %s) nounwind {
+; CHECK-LABEL: v2i64st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v0.2d, #-2.00000000
+; CHECK-NEXT: mov v0.d[1], x1
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%v = insertelement <2 x i64> <i64 13835058055282163712, i64 undef>, i64 %s, i32 1
store <2 x i64> %v, <2 x i64>* %p, align 16
ret void
-
-; CHECK-LABEL: v2i64st:
-; CHECK: fmov v[[R:[0-9]+]].2d, #-2.0
-; CHECK: mov v[[R]].d[1], x{{[0-9]+}}
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
define void @v2f32st(<2 x float>* %p, float %s) nounwind {
+; CHECK-LABEL: v2f32st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2s, #64, lsl #24
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: mov v1.s[1], v0.s[0]
+; CHECK-NEXT: str d1, [x0]
+; CHECK-NEXT: ret
%v = insertelement <2 x float> <float 2.0, float undef>, float %s, i32 1
store <2 x float> %v, <2 x float>* %p, align 8
ret void
-
-; CHECK-LABEL: v2f32st:
-; CHECK: movi v[[R:[0-9]+]].2s, #64, lsl #24
-; CHECK: mov v[[R]].s[1], v{{[0-9]+}}.s[0]
-; CHECK: str d[[R]], [x{{[0-9]+}}]
}
define void @v4f32st(<4 x float>* %p, float %s) nounwind {
+; CHECK-LABEL: v4f32st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.4s, #192, lsl #24
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-NEXT: str q1, [x0]
+; CHECK-NEXT: ret
%v = insertelement <4 x float> <float -2.0, float -2.0, float -2.0, float undef>, float %s, i32 3
store <4 x float> %v, <4 x float>* %p, align 16
ret void
-
-; CHECK-LABEL: v4f32st:
-; CHECK: movi v[[R:[0-9]+]].4s, #192, lsl #24
-; CHECK: mov v[[R]].s[3], v{{[0-9]+}}.s[0]
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
define void @v2f64st(<2 x double>* %p, double %s) nounwind {
+; CHECK-LABEL: v2f64st:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov v1.2d, #2.00000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: str q1, [x0]
+; CHECK-NEXT: ret
%v = insertelement <2 x double> <double 2.0, double undef>, double %s, i32 1
store <2 x double> %v, <2 x double>* %p, align 16
ret void
-
-; CHECK-LABEL: v2f64st:
-; CHECK: fmov v[[R:[0-9]+]].2d, #2.0
-; CHECK: mov v[[R]].d[1], v{{[0-9]+}}.d[0]
-; CHECK: str q[[R]], [x{{[0-9]+}}]
}
; In this test the illegal type has a preferred alignment greater than the
; stack alignment, that gets reduced to the alignment of a broken down
; legal type.
define <32 x i8> @test_lanex_32xi8(<32 x i8> %a, i32 %x) {
-; CHECK-LABEL: test_lanex_32xi8
-; CHECK: stp q0, q1, [sp, #-32]!
-; CHECK: ldp q0, q1, [sp], #32
+; CHECK-LABEL: test_lanex_32xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: stp q0, q1, [sp, #-32]!
+; CHECK-NEXT: and x8, x0, #0x1f
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: mov w10, #30
+; CHECK-NEXT: strb w10, [x9, x8]
+; CHECK-NEXT: ldp q0, q1, [sp], #32
+; CHECK-NEXT: ret
%b = insertelement <32 x i8> %a, i8 30, i32 %x
ret <32 x i8> %b
}
diff --git a/llvm/test/CodeGen/AArch64/dag-combine-select.ll b/llvm/test/CodeGen/AArch64/dag-combine-select.ll
index 45b998d9136d..5e0eb803f4a9 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-select.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-select.ll
@@ -1,16 +1,17 @@
-; RUN: llc -disable-post-ra -o - %s | FileCheck %s
-target triple = "arm64--"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple arm64-none-eabi -o - %s | FileCheck %s
@out = internal global i32 0, align 4
; Ensure that we transform select(C0, x, select(C1, x, y)) towards
; select(C0 | C1, x, y) so we can use CMP;CCMP for the implementation.
-; CHECK-LABEL: test0:
-; CHECK: cmp w0, #7
-; CHECK: ccmp w1, #0, #0, ne
-; CHECK: csel w0, w1, w2, gt
-; CHECK: ret
define i32 @test0(i32 %v0, i32 %v1, i32 %v2) {
+; CHECK-LABEL: test0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #7
+; CHECK-NEXT: ccmp w1, #0, #0, ne
+; CHECK-NEXT: csel w0, w1, w2, gt
+; CHECK-NEXT: ret
%cmp1 = icmp eq i32 %v0, 7
%cmp2 = icmp sgt i32 %v1, 0
%sel0 = select i1 %cmp1, i32 %v1, i32 %v2
@@ -21,19 +22,19 @@ define i32 @test0(i32 %v0, i32 %v1, i32 %v2) {
; Usually we keep select(C0 | C1, x, y) as is on aarch64 to create CMP;CCMP
; sequences. This case should be transformed to select(C0, select(C1, x, y), y)
; anyway to get CSE effects.
-; CHECK-LABEL: test1:
-; CHECK-NOT: ccmp
-; CHECK: cmp w0, #7
-; CHECK: adrp x[[OUTNUM:[0-9]+]], out
-; CHECK: csel w[[SEL0NUM:[0-9]+]], w1, w2, eq
-; CHECK: cmp w[[SEL0NUM]], #13
-; CHECK: csel w[[SEL1NUM:[0-9]+]], w1, w2, lo
-; CHECK: cmp w0, #42
-; CHECK: csel w[[SEL2NUM:[0-9]+]], w1, w[[SEL1NUM]], eq
-; CHECK: str w[[SEL1NUM]], [x[[OUTNUM]], :lo12:out]
-; CHECK: str w[[SEL2NUM]], [x[[OUTNUM]], :lo12:out]
-; CHECK: ret
define void @test1(i32 %bitset, i32 %val0, i32 %val1) {
+; CHECK-LABEL: test1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #7
+; CHECK-NEXT: csel w9, w1, w2, eq
+; CHECK-NEXT: cmp w9, #13
+; CHECK-NEXT: csel w9, w1, w2, lo
+; CHECK-NEXT: cmp w0, #42
+; CHECK-NEXT: adrp x8, out
+; CHECK-NEXT: csel w10, w1, w9, eq
+; CHECK-NEXT: str w9, [x8, :lo12:out]
+; CHECK-NEXT: str w10, [x8, :lo12:out]
+; CHECK-NEXT: ret
%cmp1 = icmp eq i32 %bitset, 7
%cond = select i1 %cmp1, i32 %val0, i32 %val1
%cmp5 = icmp ult i32 %cond, 13
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