[llvm] 09d0fa3 - [Test] Add tests showing missed opportunity for SimplifyCFG for switches

[Max Kazantsev via llvm-commits]

Author: Max Kazantsev
Date: 2021-09-10T11:16:13+07:00
New Revision: 09d0fa3bbe121b25af7773951b99f0adcab32fc0

URL: https://github.com/llvm/llvm-project/commit/09d0fa3bbe121b25af7773951b99f0adcab32fc0
DIFF: https://github.com/llvm/llvm-project/commit/09d0fa3bbe121b25af7773951b99f0adcab32fc0.diff

LOG: [Test] Add tests showing missed opportunity for SimplifyCFG for switches

Patch by Dmitry Bakunevich!

Added: 
    llvm/test/Transforms/SimplifyCFG/switch_ub.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SimplifyCFG/switch_ub.ll b/llvm/test/Transforms/SimplifyCFG/switch_ub.ll
new file mode 100644
index 0000000000000..d0d8088977776
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/switch_ub.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+; RUN: opt < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+
+; TODO: Basing on fact that load(null) is UB, we can remove edge pred->bb.
+define i32 @test_01(i32* %p, i32 %x, i1 %cond) {
+; CHECK-LABEL: @test_01(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[BB:%.*]], label [[PRED:%.*]]
+; CHECK:       pred:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[COMMON_RET:%.*]] [
+; CHECK-NEXT:    i32 42, label [[BB]]
+; CHECK-NEXT:    i32 123456, label [[BB]]
+; CHECK-NEXT:    i32 -654321, label [[BB]]
+; CHECK-NEXT:    ]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[R:%.*]], [[BB]] ], [ 0, [[PRED]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i32* [ null, [[PRED]] ], [ null, [[PRED]] ], [ null, [[PRED]] ], [ [[P:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[R]] = load i32, i32* [[PHI]], align 4
+; CHECK-NEXT:    br label [[COMMON_RET]]
+;
+entry:
+  br i1 %cond, label %bb, label %pred
+
+pred:
+  switch i32 %x, label %other_succ [i32 42, label %bb
+  i32 123456, label %bb
+  i32 -654321, label %bb]
+
+bb:
+  %phi = phi i32* [null, %pred], [null, %pred], [null, %pred], [%p, %entry]
+  %r = load i32, i32* %phi
+  ret i32 %r
+
+other_succ:
+  ret i32 0
+}
+
+; TODO: Basing on fact that load(null) is UB, we can remove edge pred->bb.
+define i32 @test_02(i32* %p, i32 %x, i1 %cond) {
+; CHECK-LABEL: @test_02(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[BB:%.*]], label [[PRED:%.*]]
+; CHECK:       pred:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[BB]] [
+; CHECK-NEXT:    i32 42, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 123456, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -654321, label [[COMMON_RET]]
+; CHECK-NEXT:    ]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[R:%.*]], [[BB]] ], [ 0, [[PRED]] ], [ 0, [[PRED]] ], [ 0, [[PRED]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i32* [ null, [[PRED]] ], [ [[P:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[R]] = load i32, i32* [[PHI]], align 4
+; CHECK-NEXT:    br label [[COMMON_RET]]
+;
+entry:
+  br i1 %cond, label %bb, label %pred
+
+pred:
+  switch i32 %x, label %bb [i32 42, label %other_succ
+  i32 123456, label %other_succ
+  i32 -654321, label %other_succ]
+
+bb:
+  %phi = phi i32* [null, %pred], [%p, %entry]
+  %r = load i32, i32* %phi
+  ret i32 %r
+
+other_succ:
+  ret i32 0
+}