[llvm] 7f48a8a - [AMDGPU] Make fexp.ll test autogenerated
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 9 12:54:30 PDT 2021
Author: Joe Nash
Date: 2021-09-09T15:37:28-04:00
New Revision: 7f48a8aedea7551318f021db5301b481e66712fb
URL: https://github.com/llvm/llvm-project/commit/7f48a8aedea7551318f021db5301b481e66712fb
DIFF: https://github.com/llvm/llvm-project/commit/7f48a8aedea7551318f021db5301b481e66712fb.diff
LOG: [AMDGPU] Make fexp.ll test autogenerated
This test is very verbose and appears generated by a script.
Make it truly autogenerated for easy updates.
NFC
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D109530
Change-Id: I1352b17b6d13ab9c5650dbe95ef0da97f71f1930
Added:
Modified:
llvm/test/CodeGen/AMDGPU/fexp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/fexp.ll b/llvm/test/CodeGen/AMDGPU/fexp.ll
index 52e177a3adccc..ba595f65bc572 100644
--- a/llvm/test/CodeGen/AMDGPU/fexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fexp.ll
@@ -1,28 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
;RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
;RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
define float @v_exp_f32(float %arg0) {
-; SI-LABEL: v_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
-; SI-NEXT: v_exp_f32_e32 v0, v0
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
-; VI-NEXT: v_exp_f32_e32 v0, v0
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_exp_f32:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_exp_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GCN-NEXT: v_exp_f32_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.exp.f32(float %arg0)
ret float %result
}
@@ -31,9 +18,9 @@ define <2 x float> @v_exp_v2f32(<2 x float> %arg0) {
; GCN-LABEL: v_exp_v2f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 [[SREG:s[0-9]+]], 0x3fb8aa3b
-; GCN-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
-; GCN-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
+; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
+; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
+; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_exp_f32_e32 v1, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -45,33 +32,32 @@ define <3 x float> @v_exp_v3f32(<3 x float> %arg0) {
; GCN-LABEL: v_exp_v3f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 [[SREG:s[0-9]+]], 0x3fb8aa3b
-; GCN-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
-; GCN-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
-; GCN-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
+; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
+; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
+; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_exp_f32_e32 v1, v1
; GCN-NEXT: v_exp_f32_e32 v2, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
%result = call <3 x float> @llvm.exp.v3f32(<3 x float> %arg0)
ret <3 x float> %result
}
define <4 x float> @v_exp_v4f32(<4 x float> %arg0) {
-; SI-LABEL: v_exp_v4f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 [[SREG:s[0-9]+]], 0x3fb8aa3b
-; SI-NEXT: v_mul_f32_e32 v0, [[SREG]], v0
-; SI-NEXT: v_mul_f32_e32 v1, [[SREG]], v1
-; SI-NEXT: v_mul_f32_e32 v2, [[SREG]], v2
-; SI-NEXT: v_mul_f32_e32 v3, [[SREG]], v3
-; SI-NEXT: v_exp_f32_e32 v0, v0
-; SI-NEXT: v_exp_f32_e32 v1, v1
-; SI-NEXT: v_exp_f32_e32 v2, v2
-; SI-NEXT: v_exp_f32_e32 v3, v3
-; SI-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_exp_v4f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
+; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
+; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v3, s4, v3
+; GCN-NEXT: v_exp_f32_e32 v0, v0
+; GCN-NEXT: v_exp_f32_e32 v1, v1
+; GCN-NEXT: v_exp_f32_e32 v2, v2
+; GCN-NEXT: v_exp_f32_e32 v3, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x float> @llvm.exp.v4f32(<4 x float> %arg0)
ret <4 x float> %result
}
@@ -109,11 +95,11 @@ define <2 x half> @v_exp_v2f16(<2 x half> %arg0) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 [[SREG:s[0-9]+]], 0x3fb8aa3b
+; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
-; SI-NEXT: v_mul_f32_e32 v{{[0-9]+}}, [[SREG]], v{{[0-9]+}}
+; SI-NEXT: v_mul_f32_e32 v0, s4, v0
+; SI-NEXT: v_mul_f32_e32 v1, s4, v1
; SI-NEXT: v_exp_f32_e32 v0, v0
; SI-NEXT: v_exp_f32_e32 v1, v1
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -121,20 +107,20 @@ define <2 x half> @v_exp_v2f16(<2 x half> %arg0) {
; VI-LABEL: v_exp_v2f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_movk_i32 [[SREG:s[0-9]+]], 0x3dc5
-; VI-NEXT: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
-; VI-NEXT: v_mul_f16_sdwa [[MUL1:v[0-9]+]], v{{[0-9]+}}, [[VREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v{{[0-9]+}}
-; VI-NEXT: v_exp_f16_sdwa [[MUL1]], [[MUL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; VI-NEXT: v_exp_f16_e32 [[MUL2]], [[MUL2]]
-; VI-NEXT: v_or_b32_e32 v{{[0-9]+}}, [[MUL2]], [[MUL1]]
+; VI-NEXT: s_movk_i32 s4, 0x3dc5
+; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_mul_f16_e32 v0, s4, v0
+; VI-NEXT: v_exp_f16_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-NEXT: v_exp_f16_e32 v0, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_exp_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 [[SREG:s[0-9]+]], 0x3dc5
-; GFX9-NEXT: v_pk_mul_f16 v0, v0, [[SREG]] op_sel_hi:[1,0]
+; GFX9-NEXT: s_movk_i32 s4, 0x3dc5
+; GFX9-NEXT: v_pk_mul_f16 v0, v0, s4 op_sel_hi:[1,0]
; GFX9-NEXT: v_exp_f16_e32 v1, v0
; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_pack_b32_f16 v0, v1, v0
@@ -156,15 +142,15 @@ define <4 x half> @v_exp_v4f16(<4 x half> %arg0) {
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 [[SREG:s[0-9]+]], 0x3fb8aa3b
+; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_mul_f32_e32 v0, [[SREG]], v0
-; SI-NEXT: v_mul_f32_e32 v1, [[SREG]], v1
-; SI-NEXT: v_mul_f32_e32 v2, [[SREG]], v2
-; SI-NEXT: v_mul_f32_e32 v3, [[SREG]], v3
+; SI-NEXT: v_mul_f32_e32 v0, s4, v0
+; SI-NEXT: v_mul_f32_e32 v1, s4, v1
+; SI-NEXT: v_mul_f32_e32 v2, s4, v2
+; SI-NEXT: v_mul_f32_e32 v3, s4, v3
; SI-NEXT: v_exp_f32_e32 v0, v0
; SI-NEXT: v_exp_f32_e32 v1, v1
; SI-NEXT: v_exp_f32_e32 v2, v2
@@ -174,34 +160,34 @@ define <4 x half> @v_exp_v4f16(<4 x half> %arg0) {
; VI-LABEL: v_exp_v4f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_movk_i32 [[SREG:s[0-9]+]], 0x3dc5
-; VI-NEXT: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
-; VI-NEXT: v_mul_f16_e32 [[MUL1:v[0-9]+]], [[SREG]], v1
-; VI-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v0
-; VI-NEXT: v_mul_f16_sdwa [[MUL3:v[0-9]+]], v1, [[VREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mul_f16_sdwa [[MUL4:v[0-9]+]], v0, [[VREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_exp_f16_e32 [[EXP1:v[0-9]+]], [[MUL1]]
-; VI-NEXT: v_exp_f16_sdwa [[EXP2:v[0-9]+]], v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; VI-NEXT: v_exp_f16_e32 [[EXP3:v[0-9]+]], [[MUL2]]
-; VI-NEXT: v_exp_f16_sdwa [[EXP4:v[0-9]+]], v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v1, [[EXP1]], [[EXP2]]
-; VI-NEXT: v_or_b32_e32 v0, [[EXP3]], [[EXP4]]
+; VI-NEXT: s_movk_i32 s4, 0x3dc5
+; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mul_f16_e32 v2, s4, v1
+; VI-NEXT: v_mul_f16_e32 v4, s4, v0
+; VI-NEXT: v_mul_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_exp_f16_e32 v2, v2
+; VI-NEXT: v_exp_f16_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-NEXT: v_exp_f16_e32 v4, v4
+; VI-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_or_b32_e32 v0, v4, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_exp_v4f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 [[SREG:s[0-9]+]], 0x3dc5
-; GFX9-NEXT: v_mul_f16_e32 [[MUL1:v[0-9]+]], [[SREG]], v1
-; GFX9-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v0
-; GFX9-NEXT: v_mul_f16_sdwa [[MUL3:v[0-9]+]], v1, [[SREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_mul_f16_sdwa [[MUL4:v[0-9]+]], v0, [[SREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_exp_f16_e32 [[EXP1:v[0-9]+]], [[MUL1]]
-; GFX9-NEXT: v_exp_f16_e32 [[EXP2:v[0-9]+]], [[MUL3]]
-; GFX9-NEXT: v_exp_f16_e32 [[EXP3:v[0-9]+]], [[MUL2]]
-; GFX9-NEXT: v_exp_f16_e32 [[EXP4:v[0-9]+]], [[MUL4]]
-; GFX9-NEXT: v_pack_b32_f16 v1, [[EXP1]], [[EXP2]]
-; GFX9-NEXT: v_pack_b32_f16 v0, [[EXP3]], [[EXP4]]
+; GFX9-NEXT: s_movk_i32 s4, 0x3dc5
+; GFX9-NEXT: v_mul_f16_e32 v2, s4, v1
+; GFX9-NEXT: v_mul_f16_e32 v3, s4, v0
+; GFX9-NEXT: v_mul_f16_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_exp_f16_e32 v2, v2
+; GFX9-NEXT: v_exp_f16_e32 v1, v1
+; GFX9-NEXT: v_exp_f16_e32 v3, v3
+; GFX9-NEXT: v_exp_f16_e32 v0, v0
+; GFX9-NEXT: v_pack_b32_f16 v1, v2, v1
+; GFX9-NEXT: v_pack_b32_f16 v0, v3, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x half> @llvm.exp.v4f16(<4 x half> %arg0)
ret <4 x half> %result
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