[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

Andrew Savonichev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 9 12:12:37 PDT 2021


asavonic added a comment.

In D107160#2917852 <https://reviews.llvm.org/D107160#2917852>, @paquette wrote:

> If it's possible to handle this using AssertZExt on the SDAG side, I think it would be nice to handle it similarly on the GISel side using G_ASSERT_ZEXT.

Can you please check if the GISel changes are fine?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107160/new/

https://reviews.llvm.org/D107160



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