[PATCH] D97435: [Aarch64] Correct register class for pseudo instructions

[Jameson Nash via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe20f69f612dd: [Aarch64] Correct register class for pseudo instructions (authored by vtjnash).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97435/new/

https://reviews.llvm.org/D97435

Files:
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-gv-with-offset.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select.mir
  llvm/test/CodeGen/AArch64/elim-dead-mi.mir
  llvm/test/CodeGen/AArch64/loop-sink.mir

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