[PATCH] D109515: [AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG

[Anton Afanasyev via Phabricator via llvm-commits]

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Add `udiv` and `urem` instructions to the DAG post-dominated by `trunc`,
allowing TruncInstCombine to reduce bitwidth of expressions containing these
instructions. It is sufficient to require that all truncated bits of both
operands are zeros: https://alive2.llvm.org/ce/z/yiithn
(`urem` case is identical).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109515

Files:
  llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/trunc_udivrem.ll

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