[llvm] ac4896e - [GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-09-08T10:09:02-07:00
New Revision: ac4896e2f37296ef47aa6f03723d275de23180f7

URL: https://github.com/llvm/llvm-project/commit/ac4896e2f37296ef47aa6f03723d275de23180f7
DIFF: https://github.com/llvm/llvm-project/commit/ac4896e2f37296ef47aa6f03723d275de23180f7.diff

LOG: [GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero

Similar to `DAGCombiner::visitRotate`.

This makes `rotl_bitwidth_cst` in postlegalizercombiner-rotate.mir reduce down
to a COPY. Modify the checkline to make sure that only rotate_out_of_range
runs there.

Differential Revision: https://reviews.llvm.org/D109264

Added: 
    

Modified: 
    llvm/include/llvm/Target/GlobalISel/Combine.td
    llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
    llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 1808aa6e6e66a..519edbe043de8 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -281,7 +281,7 @@ def select_constant_cmp: GICombineRule<
 def right_identity_zero: GICombineRule<
   (defs root:$root),
   (match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR,
-                           G_PTR_ADD):$root,
+                           G_PTR_ADD, G_ROTL, G_ROTR):$root,
     [{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]),
   (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
 >;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
index eef80e054dcd4..6a130a2192ab4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombinerhelper-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s
+# REQUIRES: asserts
 
 # Check that we simplify the constant rotate amount to be in range.
 ---

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
index 55e63ba01d35e..9551526e1fce1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
@@ -325,3 +325,39 @@ body:             |
     %op:_(p0) = G_PTR_ADD %x(p0), %cst
     $x0 = COPY %op(p0)
     RET_ReallyLR implicit $x0
+...
+---
+name:            right_identity_rotl
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+    ; CHECK-LABEL: name: right_identity_rotl
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:_(s32) = COPY $w0
+    ; CHECK: $w0 = COPY %copy(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %copy:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %rot:_(s32) = G_ROTL %copy(s32), %zero(s32)
+    $w0 = COPY %rot(s32)
+    RET_ReallyLR implicit $w0
+...
+...
+---
+name:            right_identity_rotr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+    ; CHECK-LABEL: name: right_identity_rotr
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:_(s32) = COPY $w0
+    ; CHECK: $w0 = COPY %copy(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %copy:_(s32) = COPY $w0
+    %zero:_(s32) = G_CONSTANT i32 0
+    %rot:_(s32) = G_ROTR %copy(s32), %zero(s32)
+    $w0 = COPY %rot(s32)
+    RET_ReallyLR implicit $w0
+...