[PATCH] D109323: [AArch64] Improve adrp schedule modelling on the Cortex-A55

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy updated this revision to Diff 371345.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109323/new/

https://reviews.llvm.org/D109323

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/CodeGen/AArch64/a55-fuse-address.mir


Index: llvm/test/CodeGen/AArch64/a55-fuse-address.mir
===================================================================
--- llvm/test/CodeGen/AArch64/a55-fuse-address.mir
+++ llvm/test/CodeGen/AArch64/a55-fuse-address.mir
@@ -11,8 +11,8 @@
   ; CHECK-LABEL: fuseaddress:
   ; CHECK:       // %bb.0: // %entry
   ; CHECK-NEXT:    adrp x8, a
-  ; CHECK-NEXT:    adrp x9, b
   ; CHECK-NEXT:    ldr w8, [x8, :lo12:a]
+  ; CHECK-NEXT:    adrp x9, b
   ; CHECK-NEXT:    ldr w9, [x9, :lo12:b]
   ; CHECK-NEXT:    mul w8, w8, w0
   ; CHECK-NEXT:    mul w0, w8, w9
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -616,6 +616,7 @@
                                    FeatureRCPC,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
+                                   FeatureFuseAddress,
                                    ]>;
 
 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",


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