[llvm] b041b61 - [InstCombine] add test for zext with 'or' op; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 8 06:58:13 PDT 2021
Author: Sanjay Patel
Date: 2021-09-08T09:58:06-04:00
New Revision: b041b613e6fff713fc9ad6dbc73024286fb2fc93
URL: https://github.com/llvm/llvm-project/commit/b041b613e6fff713fc9ad6dbc73024286fb2fc93
DIFF: https://github.com/llvm/llvm-project/commit/b041b613e6fff713fc9ad6dbc73024286fb2fc93.diff
LOG: [InstCombine] add test for zext with 'or' op; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/zext.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll
index a5d58430b5eb..5af31fed042b 100644
--- a/llvm/test/Transforms/InstCombine/zext.ll
+++ b/llvm/test/Transforms/InstCombine/zext.ll
@@ -431,3 +431,24 @@ define i32 @zext_or_masked_bit_test(i32 %a, i32 %b, i32 %x) {
ret i32 %z
}
+define i32 @zext_or_masked_bit_test_uses(i32 %a, i32 %b, i32 %x) {
+; CHECK-LABEL: @zext_or_masked_bit_test_uses(
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[B:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[A:%.*]]
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[B]]
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[TOBOOL]], [[CMP]]
+; CHECK-NEXT: call void @use1(i1 [[OR]])
+; CHECK-NEXT: [[Z34:%.*]] = or i1 [[TOBOOL]], [[CMP]]
+; CHECK-NEXT: [[Z3:%.*]] = zext i1 [[Z34]] to i32
+; CHECK-NEXT: ret i32 [[Z3]]
+;
+ %shl = shl i32 1, %b
+ %and = and i32 %shl, %a
+ %tobool = icmp ne i32 %and, 0
+ %cmp = icmp eq i32 %x, %b
+ %or = or i1 %tobool, %cmp
+ call void @use1(i1 %or)
+ %z = zext i1 %or to i32
+ ret i32 %z
+}
More information about the llvm-commits
mailing list