[llvm] d8d24c6 - [DAG] Fix GT -> GE condition when creating SetCC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 8 04:42:17 PDT 2021
Author: David Green
Date: 2021-09-08T12:41:51+01:00
New Revision: d8d24c64fe21948d0d4faf60e7a0ce6ba21b0b1a
URL: https://github.com/llvm/llvm-project/commit/d8d24c64fe21948d0d4faf60e7a0ce6ba21b0b1a
DIFF: https://github.com/llvm/llvm-project/commit/d8d24c64fe21948d0d4faf60e7a0ce6ba21b0b1a.diff
LOG: [DAG] Fix GT -> GE condition when creating SetCC
79845ed6dfc6511f99 folded some setcc(ashr) conditions to setcc, but got
the condition for NE incorrect, using GT where it should be using GE.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AArch64/select-constant-xor.ll
llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
llvm/test/CodeGen/ARM/select-constant-xor.ll
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/X86/select-constant-xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 28996cc06fb3a..3c77ae86d3f9a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3918,7 +3918,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
N1C && N1C->isAllOnesValue()) {
return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(0, dl, OpVT),
- Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGT);
+ Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGE);
}
if (SDValue V =
diff --git a/llvm/test/CodeGen/AArch64/select-constant-xor.ll b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
index 905eb0eff8381..023df0c2a6487 100644
--- a/llvm/test/CodeGen/AArch64/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
@@ -111,7 +111,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK-LABEL: icmpasrne:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: csel w0, w1, w2, gt
+; CHECK-NEXT: csel w0, w1, w2, ge
; CHECK-NEXT: ret
%sh = ashr i32 %input, 31
%c = icmp ne i32 %sh, -1
diff --git a/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
index 49523053f00b4..ea2c9fda56e2a 100644
--- a/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
@@ -131,7 +131,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; CHECK-NEXT: s_setpc_b64 s[30:31]
%sh = ashr i32 %input, 31
diff --git a/llvm/test/CodeGen/ARM/select-constant-xor.ll b/llvm/test/CodeGen/ARM/select-constant-xor.ll
index 9e526dfa85c0f..543ddcd3efac9 100644
--- a/llvm/test/CodeGen/ARM/select-constant-xor.ll
+++ b/llvm/test/CodeGen/ARM/select-constant-xor.ll
@@ -320,7 +320,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK7A-LABEL: icmpasrne:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: cmp r0, #0
+; CHECK7A-NEXT: cmn r0, #1
; CHECK7A-NEXT: movle r1, r2
; CHECK7A-NEXT: mov r0, r1
; CHECK7A-NEXT: bx lr
@@ -328,7 +328,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK6M-LABEL: icmpasrne:
; CHECK6M: @ %bb.0:
; CHECK6M-NEXT: cmp r0, #0
-; CHECK6M-NEXT: bgt .LBB9_2
+; CHECK6M-NEXT: bge .LBB9_2
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: mov r1, r2
; CHECK6M-NEXT: .LBB9_2:
@@ -337,7 +337,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
;
; CHECK7M-LABEL: icmpasrne:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: cmp r0, #0
+; CHECK7M-NEXT: cmp.w r0, #-1
; CHECK7M-NEXT: it le
; CHECK7M-NEXT: movle r1, r2
; CHECK7M-NEXT: mov r0, r1
@@ -345,7 +345,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
;
; CHECK81M-LABEL: icmpasrne:
; CHECK81M: @ %bb.0:
-; CHECK81M-NEXT: cmp r0, #0
+; CHECK81M-NEXT: cmp.w r0, #-1
; CHECK81M-NEXT: csel r0, r1, r2, gt
; CHECK81M-NEXT: bx lr
%sh = ashr i32 %input, 31
diff --git a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
index 6feb195f9ac63..0f77ca6a58d25 100644
--- a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
@@ -117,7 +117,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK-LABEL: icmpasrne:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmpwi 3, 0
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: iselgt 3, 4, 5
; CHECK-NEXT: blr
%sh = ashr i32 %input, 31
diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
index a9b26b63f2bb5..ddda22fcf9804 100644
--- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll
+++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
@@ -188,7 +188,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK32-LABEL: icmpasrne:
; CHECK32: # %bb.0:
-; CHECK32-NEXT: bgtz a0, .LBB9_2
+; CHECK32-NEXT: bgez a0, .LBB9_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: mv a1, a2
; CHECK32-NEXT: .LBB9_2:
@@ -199,7 +199,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: sext.w a3, a0
; CHECK64-NEXT: mv a0, a1
-; CHECK64-NEXT: bgtz a3, .LBB9_2
+; CHECK64-NEXT: bgez a3, .LBB9_2
; CHECK64-NEXT: # %bb.1:
; CHECK64-NEXT: mv a0, a2
; CHECK64-NEXT: .LBB9_2:
diff --git a/llvm/test/CodeGen/X86/select-constant-xor.ll b/llvm/test/CodeGen/X86/select-constant-xor.ll
index 4b45b66b7e938..7f8f9bbf6148e 100644
--- a/llvm/test/CodeGen/X86/select-constant-xor.ll
+++ b/llvm/test/CodeGen/X86/select-constant-xor.ll
@@ -124,7 +124,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: cmovlel %edx, %eax
+; CHECK-NEXT: cmovsl %edx, %eax
; CHECK-NEXT: retq
%sh = ashr i32 %input, 31
%c = icmp ne i32 %sh, -1
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