[PATCH] D108288: [LegalizeTypes][VP] Add promotion support for binary VP ops

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll:15
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vadd.vv v26, v26, v26
----------------
frasercrmck wrote:
> craig.topper wrote:
> > We should use slli a0, a0, 1 followed by vmv.v.x here. Not something that needs to be fixed in this patch though.
> Ah yes that's an interesting observation. Presumably we also want to do the `vsra.vi v26, v26, 1` in scalar before splatting?
That said, the ideal is surely just to do `vdiv.vx` with `a0`? The fixed vectors generate:
```
        vsetivli        zero, 8, e8, mf2, ta, mu
        vadd.vv v25, v8, v8
        vsra.vi v25, v25, 1
        vsetvli zero, a1, e8, mf2, ta, mu
        vdiv.vx v8, v25, a0, v0.t
```
I'll look into what's going on.


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  https://reviews.llvm.org/D108288/new/

https://reviews.llvm.org/D108288