[llvm] f0460fa - [AArch64] Improve target hook function to decide folding (mul (add x, c1), c2)
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 7 18:51:38 PDT 2021
Author: Ben Shi
Date: 2021-09-08T01:51:26Z
New Revision: f0460fa4eb719f621fc0ec971d55b530d90a58e1
URL: https://github.com/llvm/llvm-project/commit/f0460fa4eb719f621fc0ec971d55b530d90a58e1
DIFF: https://github.com/llvm/llvm-project/commit/f0460fa4eb719f621fc0ec971d55b530d90a58e1.diff
LOG: [AArch64] Improve target hook function to decide folding (mul (add x, c1), c2)
Prevent the folding if it leads to worse code.
Reviewed By: dmgreen, kda
Differential Revision: https://reviews.llvm.org/D108871
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/addimm-mulimm.ll
llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 83254b392750..e99b16c82314 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12190,6 +12190,33 @@ bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
return IsLegal;
}
+// Return false to prevent folding
+// (mul (add x, c1), c2) -> (add (mul x, c2), c2*c1) in DAGCombine,
+// if the folding leads to worse code.
+bool AArch64TargetLowering::isMulAddWithConstProfitable(
+ const SDValue &AddNode, const SDValue &ConstNode) const {
+ // Let the DAGCombiner decide for vector types and large types.
+ const EVT VT = AddNode.getValueType();
+ if (VT.isVector() || VT.getScalarSizeInBits() > 64)
+ return true;
+
+ // It is worse if c1 is legal add immediate, while c1*c2 is not
+ // and has to be composed by at least two instructions.
+ const ConstantSDNode *C1Node = cast<ConstantSDNode>(AddNode.getOperand(1));
+ const ConstantSDNode *C2Node = cast<ConstantSDNode>(ConstNode);
+ const int64_t C1 = C1Node->getSExtValue();
+ const APInt C1C2 = C1Node->getAPIntValue() * C2Node->getAPIntValue();
+ if (!isLegalAddImmediate(C1) || isLegalAddImmediate(C1C2.getSExtValue()))
+ return true;
+ SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
+ AArch64_IMM::expandMOVImm(C1C2.getZExtValue(), VT.getSizeInBits(), Insn);
+ if (Insn.size() > 1)
+ return false;
+
+ // Default to true and let the DAGCombiner decide.
+ return true;
+}
+
// Integer comparisons are implemented with ADDS/SUBS, so the range of valid
// immediates is the same as for an add or a sub.
bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index ac805c2257ad..00ed3171ccba 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -595,6 +595,9 @@ class AArch64TargetLowering : public TargetLowering {
bool isLegalAddImmediate(int64_t) const override;
bool isLegalICmpImmediate(int64_t) const override;
+ bool isMulAddWithConstProfitable(const SDValue &AddNode,
+ const SDValue &ConstNode) const override;
+
bool shouldConsiderGEPOffsetSplit() const override;
EVT getOptimalMemOpType(const MemOp &Op,
diff --git a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll
index 284933bb20b2..d6ecf6e3df66 100644
--- a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll
+++ b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll
@@ -104,10 +104,9 @@ define signext i32 @addimm_mulimm_accept_13(i32 signext %a) {
define i64 @addimm_mulimm_reject_00(i64 %a) {
; CHECK-LABEL: addimm_mulimm_reject_00:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1200
-; CHECK-NEXT: mov w8, #3700
-; CHECK-NEXT: movk w9, #175, lsl #16
-; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: add x8, x0, #3100
+; CHECK-NEXT: mov w9, #3700
+; CHECK-NEXT: mul x0, x8, x9
; CHECK-NEXT: ret
%tmp0 = add i64 %a, 3100
%tmp1 = mul i64 %tmp0, 3700
@@ -117,10 +116,9 @@ define i64 @addimm_mulimm_reject_00(i64 %a) {
define i64 @addimm_mulimm_reject_01(i64 %a) {
; CHECK-LABEL: addimm_mulimm_reject_01:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x9, #-1200
-; CHECK-NEXT: mov w8, #3700
-; CHECK-NEXT: movk x9, #65360, lsl #16
-; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: sub x8, x0, #3100
+; CHECK-NEXT: mov w9, #3700
+; CHECK-NEXT: mul x0, x8, x9
; CHECK-NEXT: ret
%tmp0 = add i64 %a, -3100
%tmp1 = mul i64 %tmp0, 3700
@@ -130,10 +128,9 @@ define i64 @addimm_mulimm_reject_01(i64 %a) {
define signext i32 @addimm_mulimm_reject_02(i32 signext %a) {
; CHECK-LABEL: addimm_mulimm_reject_02:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1200
-; CHECK-NEXT: mov w8, #3700
-; CHECK-NEXT: movk w9, #175, lsl #16
-; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: add w8, w0, #3100
+; CHECK-NEXT: mov w9, #3700
+; CHECK-NEXT: mul w0, w8, w9
; CHECK-NEXT: ret
%tmp0 = add i32 %a, 3100
%tmp1 = mul i32 %tmp0, 3700
@@ -143,10 +140,9 @@ define signext i32 @addimm_mulimm_reject_02(i32 signext %a) {
define signext i32 @addimm_mulimm_reject_03(i32 signext %a) {
; CHECK-LABEL: addimm_mulimm_reject_03:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #64336
-; CHECK-NEXT: mov w8, #3700
-; CHECK-NEXT: movk w9, #65360, lsl #16
-; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: sub w8, w0, #3100
+; CHECK-NEXT: mov w9, #3700
+; CHECK-NEXT: mul w0, w8, w9
; CHECK-NEXT: ret
%tmp0 = add i32 %a, -3100
%tmp1 = mul i32 %tmp0, 3700
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll b/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
index 6771882ee98f..beeb33960d4c 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
@@ -154,11 +154,10 @@ define i1 @t32_6_3(i32 %X) nounwind {
define i1 @t32_6_4(i32 %X) nounwind {
; CHECK-LABEL: t32_6_4:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #43691
-; CHECK-NEXT: mov w9, #21844
-; CHECK-NEXT: movk w8, #43690, lsl #16
-; CHECK-NEXT: movk w9, #21845, lsl #16
-; CHECK-NEXT: madd w8, w0, w8, w9
+; CHECK-NEXT: mov w9, #43691
+; CHECK-NEXT: sub w8, w0, #4
+; CHECK-NEXT: movk w9, #43690, lsl #16
+; CHECK-NEXT: mul w8, w8, w9
; CHECK-NEXT: mov w9, #43690
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: movk w9, #10922, lsl #16
@@ -173,11 +172,10 @@ define i1 @t32_6_4(i32 %X) nounwind {
define i1 @t32_6_5(i32 %X) nounwind {
; CHECK-LABEL: t32_6_5:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #43691
-; CHECK-NEXT: mov w9, #43689
-; CHECK-NEXT: movk w8, #43690, lsl #16
+; CHECK-NEXT: mov w9, #43691
+; CHECK-NEXT: sub w8, w0, #5
; CHECK-NEXT: movk w9, #43690, lsl #16
-; CHECK-NEXT: madd w8, w0, w8, w9
+; CHECK-NEXT: mul w8, w8, w9
; CHECK-NEXT: mov w9, #43690
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: movk w9, #10922, lsl #16
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