[PATCH] D109405: [RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos

[Craig Topper via Phabricator via llvm-commits]

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The expansion of these pseudos creates ADD instructions. Those
ADDs modify a GPR so that it is no longer contains the same value
as the input base pointer. Therefore, I believe we should have a
GPR as a Def on these instructions and expansion should get the
destination register for the ADDs from that operand.

At least in our tests here this works out so that register
scavenging picks the same register as the base pointer.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109405

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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