[PATCH] D109300: [AMDGPU] Make vector super classes allocatable

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can you specifically mention VGPRs and AGPRs in the commit message/description



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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:11395
+          continue;
+        auto *RC = TRI->getRegClassForReg(MRI, Op.getReg());
+        if (!Op.getReg().isVirtual() || !TRI->hasAGPRs(RC))
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Can you shortcut the getRegClassForReg if not virtual?


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  https://reviews.llvm.org/D109300/new/

https://reviews.llvm.org/D109300