[llvm] f8d2cd1 - [X86] Add missing domain to avx512_ord_cmp_sae comis sae patterns

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-09-07T16:20:21+01:00
New Revision: f8d2cd1428f58c36f1ccddaf24e52864a0f2c117

URL: https://github.com/llvm/llvm-project/commit/f8d2cd1428f58c36f1ccddaf24e52864a0f2c117
DIFF: https://github.com/llvm/llvm-project/commit/f8d2cd1428f58c36f1ccddaf24e52864a0f2c117.diff

LOG: [X86] Add missing domain to avx512_ord_cmp_sae comis sae patterns

It doesn't appear to be possible to generate this from tests atm, but it matches what we do in sse12_ord_cmp

Fixes unused template arg identified in D109359

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrAVX512.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index b4f1730cbdd1..ffa4a53e76c6 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -9239,7 +9239,7 @@ let Predicates = [HasVLX] in {
 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _,
                             string OpcodeStr, Domain d,
                             X86FoldableSchedWrite sched = WriteFComX> {
-  let hasSideEffects = 0, Uses = [MXCSR] in
+  let ExeDomain = d, hasSideEffects = 0, Uses = [MXCSR] in
   def rrb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
                   !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"), []>,
                   EVEX, EVEX_B, VEX_LIG, EVEX_V128, Sched<[sched]>;