[PATCH] D109365: [PowerPC] Guard XSRSP in P8 for FastISel

[Jinsong Ji via Phabricator via llvm-commits]

jsji created this revision.
jsji added reviewers: PowerPC, qiucf, shchenz.
Herald added subscribers: kbarton, hiraditya, nemanjai.
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This is exposed by enabling FastIsel on 64bit AIX.
We are generating XSRSP regardless of the arch,
which may be wrong when -mcpu=pwr7.

The fix is to guard the generation in P8 <https://reviews.llvm.org/P8> only.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109365

Files:
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll


Index: llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll
+++ llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll
@@ -2,6 +2,10 @@
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
 ; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -O0 < %s \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+
 
 define float @testRSP(double %x) {
 entry:
Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -987,15 +987,16 @@
   auto RC = MRI.getRegClass(SrcReg);
   if (Subtarget->hasSPE()) {
     DestReg = createResultReg(&PPC::GPRCRegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-      TII.get(PPC::EFSCFD), DestReg)
-      .addReg(SrcReg);
-  } else if (isVSFRCRegClass(RC)) {
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD),
+            DestReg)
+        .addReg(SrcReg);
+  } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
     DestReg = createResultReg(&PPC::VSSRCRegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-      TII.get(PPC::XSRSP), DestReg)
-      .addReg(SrcReg);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::XSRSP),
+            DestReg)
+        .addReg(SrcReg);
   } else {
+    SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
     DestReg = createResultReg(&PPC::F4RCRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
       TII.get(PPC::FRSP), DestReg)


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