[llvm] 448d47f - [AArch64][SVE] Implement all-inactive predicate with PFALSE.

[Sander de Smalen via llvm-commits]

Author: Sander de Smalen
Date: 2021-09-07T14:29:02+01:00
New Revision: 448d47f7438e5ca4a5cd4a77e5e78cd62333e487

URL: https://github.com/llvm/llvm-project/commit/448d47f7438e5ca4a5cd4a77e5e78cd62333e487
DIFF: https://github.com/llvm/llvm-project/commit/448d47f7438e5ca4a5cd4a77e5e78cd62333e487.diff

LOG: [AArch64][SVE] Implement all-inactive predicate with PFALSE.

Instead of using a WHILE XZR, XZR instruction, just emit a PFALSE.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D109311

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
    llvm/test/CodeGen/AArch64/sve-zeroinit.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 337c61a4b7bee..83254b3927502 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9643,9 +9643,10 @@ SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op,
     // The only legal i1 vectors are SVE vectors, so we can use SVE-specific
     // lowering code.
     if (auto *ConstVal = dyn_cast<ConstantSDNode>(SplatVal)) {
+      if (ConstVal->isNullValue())
+        return SDValue(DAG.getMachineNode(AArch64::PFALSE, dl, VT), 0);
       if (ConstVal->isOne())
         return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all);
-      // TODO: Add special case for constant false
     }
     // The general case of i1.  There isn't any natural way to do this,
     // so we use some trickery with whilelo.

diff  --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
index bb1523c131344..e1f5ff448dd60 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
@@ -1072,7 +1072,7 @@ define <vscale x 16 x i1> @wide_cmplo_b(<vscale x 16 x i1> %pg, <vscale x 16 x i
 
 define <vscale x 8 x i1> @ir_cmplo_h(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: ir_cmplo_h
-; CHECK: whilelo p0.h, xzr, xzr
+; CHECK: pfalse p0.b
 ; CHECK-NEXT: ret
   %elt   = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer

diff  --git a/llvm/test/CodeGen/AArch64/sve-zeroinit.ll b/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
index 4ae496b409fff..de7695a86ff90 100644
--- a/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
+++ b/llvm/test/CodeGen/AArch64/sve-zeroinit.ll
@@ -54,28 +54,28 @@ define <vscale x 8 x half> @test_zeroinit_8xf16() {
 
 define <vscale x 2 x i1> @test_zeroinit_2xi1() {
 ; CHECK-LABEL: test_zeroinit_2xi1
-; CHECK:       whilelo p0.d, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 2 x i1> zeroinitializer
 }
 
 define <vscale x 4 x i1> @test_zeroinit_4xi1() {
 ; CHECK-LABEL: test_zeroinit_4xi1
-; CHECK:       whilelo p0.s, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 4 x i1> zeroinitializer
 }
 
 define <vscale x 8 x i1> @test_zeroinit_8xi1() {
 ; CHECK-LABEL: test_zeroinit_8xi1
-; CHECK:       whilelo p0.h, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 8 x i1> zeroinitializer
 }
 
 define <vscale x 16 x i1> @test_zeroinit_16xi1() {
 ; CHECK-LABEL: test_zeroinit_16xi1
-; CHECK:       whilelo p0.b, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 16 x i1> zeroinitializer
 }