[PATCH] D109069: [AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts.
weiwei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 7 02:13:19 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rGda9ed3dc719b: [AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts. (authored by wwei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109069/new/
https://reviews.llvm.org/D109069
Files:
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
Index: llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
@@ -0,0 +1,21 @@
+# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
+
+---
+# CHECK-LABEL: name: test
+# CHECK-LABEL: bb.0:
+# CHECK: $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv
+# CHECK-NEXT: $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv
+# CHECK-NEXT: RET undef $lr
+#
+name: test
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w5, $w6, $x2, $x3
+
+ renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv
+ renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv
+ RET_ReallyLR
+
+...
Index: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -937,12 +937,16 @@
case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
}
- MachineInstrBuilder MIB1 =
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
- MI.getOperand(0).getReg())
- .add(MI.getOperand(1))
- .add(MI.getOperand(2))
- .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
+ MachineFunction &MF = *MBB.getParent();
+ // Try to create new inst without implicit operands added.
+ MachineInstr *NewMI = MF.CreateMachineInstr(
+ TII->get(Opcode), MI.getDebugLoc(), /*NoImplicit=*/true);
+ MBB.insert(MBBI, NewMI);
+ MachineInstrBuilder MIB1(MF, NewMI);
+ MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
+ .add(MI.getOperand(1))
+ .add(MI.getOperand(2))
+ .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
transferImpOps(MI, MIB1, MIB1);
MI.eraseFromParent();
return true;
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