[PATCH] D108961: [RISCV] MC relaxation for out-of-range conditional branch.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

> https://gcc.gnu.org/onlinedocs/gcc/Size-of-an-asm.html#Size-of-an-asm says
> "It does this by counting the number of instructions in the pattern of the asm "
> Multiple RISC ports use this. If GCC RISCV doesn't do this yet, it should be fixed.

That's not target dependent feature, and it's roughly way to estimate, unless GCC has something like MC layer, otherwise it's never accurate.

> For completeness, such long branches are typically not performance bottleneck.
> Even if linker relaxation can shorten the distance a bit and allow more short-form branches,
> it may not worth the complexity.

RISC-V don't have special relocation to handle this relaxation, and binutils didn't handle that, although that could be recognized by `R_RISCV_BRANCH` + `R_RISCV_JAL` pair, but as you said it's might be complicated and not worth.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108961/new/

https://reviews.llvm.org/D108961