[PATCH] D109323: [AArch64] Improve adrp schedule modelling on the Cortex-A55

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:3215
                            asm, pattern>,
-           Sched<[WriteLD]>;
+           Sched<[WriteLD, ReadAdrBase]>;
 
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This seems like a separate feature from adding FeatureFuseAddress for A55.

ReadAdrBase seems to be for the "base resister of a reg-offset LD/ST", where as this is the base register of a imm-offset LD/ST.
Having a Read for this would sound useful, but it would probably be best for it to be on all Imm offset base registers, not just this one, and sounds like a separate change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109323/new/

https://reviews.llvm.org/D109323