[PATCH] D109311: [AArch64][SVE] Implement all-inactive predicate with PFALSE.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
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Instead of using a WHILE XZR, XZR instruction, just emit a PFALSE.

Change-Id: I081a71293dc0990e8f4ac51418f36da33cbdaa27


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109311

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
  llvm/test/CodeGen/AArch64/sve-zeroinit.ll


Index: llvm/test/CodeGen/AArch64/sve-zeroinit.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-zeroinit.ll
+++ llvm/test/CodeGen/AArch64/sve-zeroinit.ll
@@ -54,28 +54,28 @@
 
 define <vscale x 2 x i1> @test_zeroinit_2xi1() {
 ; CHECK-LABEL: test_zeroinit_2xi1
-; CHECK:       whilelo p0.d, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 2 x i1> zeroinitializer
 }
 
 define <vscale x 4 x i1> @test_zeroinit_4xi1() {
 ; CHECK-LABEL: test_zeroinit_4xi1
-; CHECK:       whilelo p0.s, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 4 x i1> zeroinitializer
 }
 
 define <vscale x 8 x i1> @test_zeroinit_8xi1() {
 ; CHECK-LABEL: test_zeroinit_8xi1
-; CHECK:       whilelo p0.h, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 8 x i1> zeroinitializer
 }
 
 define <vscale x 16 x i1> @test_zeroinit_16xi1() {
 ; CHECK-LABEL: test_zeroinit_16xi1
-; CHECK:       whilelo p0.b, xzr, xzr
+; CHECK:       pfalse p0.b
 ; CHECK-NEXT:  ret
   ret <vscale x 16 x i1> zeroinitializer
 }
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
@@ -1072,7 +1072,7 @@
 
 define <vscale x 8 x i1> @ir_cmplo_h(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: ir_cmplo_h
-; CHECK: whilelo p0.h, xzr, xzr
+; CHECK: pfalse p0.b
 ; CHECK-NEXT: ret
   %elt   = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9643,6 +9643,8 @@
     // The only legal i1 vectors are SVE vectors, so we can use SVE-specific
     // lowering code.
     if (auto *ConstVal = dyn_cast<ConstantSDNode>(SplatVal)) {
+      if (ConstVal->isNullValue())
+        return SDValue(DAG.getMachineNode(AArch64::PFALSE, dl, VT), 0);
       if (ConstVal->isOne())
         return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all);
       // TODO: Add special case for constant false


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