[PATCH] D109301: [AMDGPU] Enable VGPR to AGPR copy during regalloc

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added reviewers: arsenm, rampitec.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, qcolombet.
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Greedy register allocator prefers to move a constrained
live range into a larger allocatable class over spilling
them. This patch defines the necessary superclasses for
VGPRs. For subtargets that support copy between VGPRs and
AGPRs, the VGPR spill during regalloc now become just copies
thereby avoiding the hack later during frame lowering that
changes the VGPR spill pseudo instruction to a copy into AGPR.

With inline asm, it is possible to make the superclasses
unavailable during allocator and we still see spills. All
vector spills, including the CSRs, will now go to memory.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109301

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/agpr-csr.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
  llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
  llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
  llvm/test/CodeGen/AMDGPU/save-fp.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr.mir
  llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir