[PATCH] D109291: [SelectionDAGBuilder] Bugfix in visitInlineAsm()

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
jonpa added reviewers: uweigand, tstellar.
Herald added subscribers: pengfei, hiraditya.
jonpa requested review of this revision.
Herald added a project: LLVM.

In case of a virtual register tied to a phys-def, the register class needs to be computed. Make sure that this works generally also with fast regalloc by using TLI.getRegClassFor() whenever possible, and make only the case of 'Untyped' use getMinimalPhysRegClass().

Fixes https://bugs.llvm.org/show_bug.cgi?id=51699


https://reviews.llvm.org/D109291

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/X86/20210831-inlineasm.ll


Index: llvm/test/CodeGen/X86/20210831-inlineasm.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/20210831-inlineasm.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -O0 -mtriple=x86_64-unknown-linux-gnu
+; https://bugs.llvm.org/show_bug.cgi?id=51699
+
+%"[]u8" = type { i8*, i64 }
+%std.mem.Allocator = type { void ({ %"[]u8", i16 }*, %std.builtin.StackTrace*, %std.mem.Allocator*, i64, i29, i29, i64)*, void ({ i64, i16 }*, %std.builtin.StackTrace*, %std.mem.Allocator*, %"[]u8"*, i29, i64, i29, i64)* }
+%std.builtin.StackTrace = type { i64, %"[]usize" }
+%"[]usize" = type { i64*, i64 }
+
+define  void @fun(%"[]u8"* %0) #0 {
+Entry:
+  %1 = alloca [6 x i64], align 8
+  br label %ErrRetContinue
+
+ErrRetContinue:                                   ; preds = %Entry
+  %2 = call i64 asm sideeffect "rolq $$3,  %rdi ; rolq $$13, %rdi\0Arolq $$61, %rdi ; rolq $$51, %rdi\0Axchgq %rbx,%rbx\0A", "={rdx},{rax},0,~{cc},~{memory}"(i64 undef, i64 0)
+  %3 = call fastcc i64 undef(%std.mem.Allocator* undef, %"[]u8"* %0, i29 undef, i64 0, i29 0, i64 undef)
+  ret void
+}
+
+attributes #0 = { sspstrong }
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8825,8 +8825,10 @@
           auto *R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]);
           Register TiedReg = R->getReg();
           MVT RegVT = R->getSimpleValueType(0);
-          const TargetRegisterClass *RC = TiedReg.isVirtual() ?
-            MRI.getRegClass(TiedReg) : TRI.getMinimalPhysRegClass(TiedReg);
+          const TargetRegisterClass *RC =
+              TiedReg.isVirtual()     ? MRI.getRegClass(TiedReg)
+              : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT)
+                                      : TRI.getMinimalPhysRegClass(TiedReg);
           unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag);
           for (unsigned i = 0; i != NumRegs; ++i)
             Regs.push_back(MRI.createVirtualRegister(RC));


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