[llvm] 8523fb9 - [DAG] Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 5 08:04:11 PDT 2021
Author: David Green
Date: 2021-09-05T16:04:01+01:00
New Revision: 8523fb96a63e9c517cb4d2d849fdde1ed65d3d26
URL: https://github.com/llvm/llvm-project/commit/8523fb96a63e9c517cb4d2d849fdde1ed65d3d26
DIFF: https://github.com/llvm/llvm-project/commit/8523fb96a63e9c517cb4d2d849fdde1ed65d3d26.diff
LOG: [DAG] Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C
Given a select_cc producing a constant and a invertion of the constant
for a comparison more than zero, we can produce an xor with ashr
instead, which produces smaller code. The ashr either sets all bits or
clear all bits depending on if the value is negative. This is then xor'd
with the constant to optionally negate the value.
https://alive2.llvm.org/ce/z/DTFaBZ
This includes a OneUseCheck on the Cmp, which seems to make thinks a
little worse and will be removed in a followup.
Differential Revision: https://reviews.llvm.org/D109149
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/select-constant-xor.ll
llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
llvm/test/CodeGen/ARM/select-constant-xor.ll
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/X86/pr16031.ll
llvm/test/CodeGen/X86/select-constant-xor.ll
llvm/test/CodeGen/X86/smul_fix_sat.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9c8febcedc59..0eb8040ef5db 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22875,6 +22875,21 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
}
}
+ // Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C
+ // Fold select_cc setlt X, 0, C, ~C -> xor (ashr X, BW-1), ~C
+ if (!NotExtCompare && N1C && N2C && N3C &&
+ N2C->getAPIntValue() == ~N3C->getAPIntValue() &&
+ ((N1C->isAllOnesValue() && CC == ISD::SETGT) ||
+ (N1C->isNullValue() && CC == ISD::SETLT)) &&
+ !TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1) &&
+ N0->hasOneUse()) {
+ SDValue ASR = DAG.getNode(
+ ISD::SRA, DL, CmpOpVT, N0,
+ DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT));
+ return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT),
+ DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT));
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/select-constant-xor.ll b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
index 79d28cdb6863..a4be02f86243 100644
--- a/llvm/test/CodeGen/AArch64/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
@@ -16,9 +16,8 @@ define i32 @xori64i32(i64 %a) {
define i64 @selecti64i64(i64 %a) {
; CHECK-LABEL: selecti64i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: mov w8, #2147483647
-; CHECK-NEXT: cinv x0, x8, lt
+; CHECK-NEXT: asr x8, x0, #63
+; CHECK-NEXT: eor x0, x8, #0x7fffffff
; CHECK-NEXT: ret
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -28,9 +27,8 @@ define i64 @selecti64i64(i64 %a) {
define i32 @selecti64i32(i64 %a) {
; CHECK-LABEL: selecti64i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: mov w8, #2147483647
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: asr x8, x0, #63
+; CHECK-NEXT: eor w0, w8, #0x7fffffff
; CHECK-NEXT: ret
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i32 2147483647, i32 -2147483648
@@ -40,9 +38,9 @@ define i32 @selecti64i32(i64 %a) {
define i64 @selecti32i64(i32 %a) {
; CHECK-LABEL: selecti32i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #2147483647
-; CHECK-NEXT: cinv x0, x8, lt
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #31, #1
+; CHECK-NEXT: eor x0, x8, #0x7fffffff
; CHECK-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -66,9 +64,8 @@ define i8 @xori32i8(i32 %a) {
define i32 @selecti32i32(i32 %a) {
; CHECK-LABEL: selecti32i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #84
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: eor w0, w8, w0, asr #31
; CHECK-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -78,9 +75,8 @@ define i32 @selecti32i32(i32 %a) {
define i8 @selecti32i8(i32 %a) {
; CHECK-LABEL: selecti32i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #84
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: eor w0, w8, w0, asr #31
; CHECK-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i8 84, i8 -85
@@ -91,9 +87,8 @@ define i32 @selecti8i32(i8 %a) {
; CHECK-LABEL: selecti8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: mov w8, #84
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: mov w9, #84
+; CHECK-NEXT: eor w0, w9, w8, asr #7
; CHECK-NEXT: ret
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -148,9 +143,8 @@ define i32 @selecti32i32_m1(i32 %a) {
define i32 @selecti32i32_1(i32 %a) {
; CHECK-LABEL: selecti32i32_1:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #1
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: asr w8, w0, #31
+; CHECK-NEXT: eor w0, w8, #0x1
; CHECK-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 1, i32 -2
@@ -160,9 +154,8 @@ define i32 @selecti32i32_1(i32 %a) {
define i32 @selecti32i32_sge(i32 %a) {
; CHECK-LABEL: selecti32i32_sge:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #12
-; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: asr w8, w0, #31
+; CHECK-NEXT: eor w0, w8, #0xc
; CHECK-NEXT: ret
%c = icmp sge i32 %a, 0
%s = select i1 %c, i32 12, i32 -13
@@ -172,9 +165,8 @@ define i32 @selecti32i32_sge(i32 %a) {
define i32 @selecti32i32_slt(i32 %a) {
; CHECK-LABEL: selecti32i32_slt:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #-13
-; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: asr w8, w0, #31
+; CHECK-NEXT: eor w0, w8, #0xc
; CHECK-NEXT: ret
%c = icmp slt i32 %a, 0
%s = select i1 %c, i32 -13, i32 12
@@ -184,9 +176,8 @@ define i32 @selecti32i32_slt(i32 %a) {
define i32 @selecti32i32_sle(i32 %a) {
; CHECK-LABEL: selecti32i32_sle:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #-13
-; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: asr w8, w0, #31
+; CHECK-NEXT: eor w0, w8, #0xc
; CHECK-NEXT: ret
%c = icmp sle i32 %a, -1
%s = select i1 %c, i32 -13, i32 12
@@ -196,9 +187,8 @@ define i32 @selecti32i32_sle(i32 %a) {
define i32 @selecti32i32_sgt(i32 %a) {
; CHECK-LABEL: selecti32i32_sgt:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: mov w8, #-13
-; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: asr w8, w0, #31
+; CHECK-NEXT: eor w0, w8, #0xc
; CHECK-NEXT: ret
%c = icmp sle i32 %a, -1
%s = select i1 %c, i32 -13, i32 12
diff --git a/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
index 217feb446fbc..49523053f00b 100644
--- a/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
@@ -20,10 +20,8 @@ define i64 @selecti64i64(i64 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]
-; CHECK-NEXT: v_bfrev_b32_e32 v2, -2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo
-; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo
+; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -35,9 +33,8 @@ define i32 @selecti64i32(i64 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]
-; CHECK-NEXT: v_bfrev_b32_e32 v2, -2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i32 2147483647, i32 -2147483648
@@ -49,10 +46,9 @@ define i64 @selecti32i64(i32 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_bfrev_b32_e32 v1, -2
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v1, vcc_lo
-; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo
+; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1
+; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -80,9 +76,8 @@ define i32 @selecti32i32(i32 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0x54
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -94,9 +89,8 @@ define i8 @selecti32i8(i32 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0x54
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i8 84, i8 -85
@@ -108,10 +102,10 @@ define i32 @selecti8i32(i8 %a) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT: v_mov_b32_e32 v1, -1
-; CHECK-NEXT: v_mov_b32_e32 v2, 0x54
-; CHECK-NEXT: v_cmp_gt_i16_sdwa vcc_lo, sext(v0), v1 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v2, vcc_lo
+; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 8
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x54
+; CHECK-NEXT: v_ashrrev_i16 v0, 7, v0
+; CHECK-NEXT: v_xor_b32_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -152,10 +146,9 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: v_mov_b32_e32 v3, 0xffffff80
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x7f, v3, vcc_lo
-; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; CHECK-NEXT: v_xad_u32 v0, 0x7f, v3, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%c = icmp sle i32 %a, -1
%s = select i1 %c, i32 -128, i32 127
diff --git a/llvm/test/CodeGen/ARM/select-constant-xor.ll b/llvm/test/CodeGen/ARM/select-constant-xor.ll
index 730d72c7415a..a16ce1656f16 100644
--- a/llvm/test/CodeGen/ARM/select-constant-xor.ll
+++ b/llvm/test/CodeGen/ARM/select-constant-xor.ll
@@ -42,54 +42,34 @@ define i32 @xori64i32(i64 %a) {
define i64 @selecti64i64(i64 %a) {
; CHECK7A-LABEL: selecti64i64:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: cmn r1, #1
-; CHECK7A-NEXT: mov r0, #-2147483648
-; CHECK7A-NEXT: mvn r1, #0
-; CHECK7A-NEXT: mvngt r0, #-2147483648
-; CHECK7A-NEXT: movwgt r1, #0
+; CHECK7A-NEXT: mvn r0, #-2147483648
+; CHECK7A-NEXT: eor r0, r0, r1, asr #31
+; CHECK7A-NEXT: asr r1, r1, #31
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti64i64:
; CHECK6M: @ %bb.0:
-; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB1_2
-; CHECK6M-NEXT: @ %bb.1:
-; CHECK6M-NEXT: movs r0, #1
-; CHECK6M-NEXT: lsls r0, r0, #31
-; CHECK6M-NEXT: b .LBB1_3
-; CHECK6M-NEXT: .LBB1_2:
+; CHECK6M-NEXT: asrs r1, r1, #31
; CHECK6M-NEXT: ldr r0, .LCPI1_0
-; CHECK6M-NEXT: .LBB1_3:
-; CHECK6M-NEXT: movs r2, #0
-; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB1_5
-; CHECK6M-NEXT: @ %bb.4:
-; CHECK6M-NEXT: mvns r2, r2
-; CHECK6M-NEXT: .LBB1_5:
-; CHECK6M-NEXT: mov r1, r2
+; CHECK6M-NEXT: eors r0, r1
; CHECK6M-NEXT: bx lr
; CHECK6M-NEXT: .p2align 2
-; CHECK6M-NEXT: @ %bb.6:
+; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: .LCPI1_0:
; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK7M-LABEL: selecti64i64:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: cmp.w r1, #-1
-; CHECK7M-NEXT: mov.w r0, #-2147483648
-; CHECK7M-NEXT: mov.w r1, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: mvngt r0, #-2147483648
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: movgt r1, #0
+; CHECK7M-NEXT: mvn r0, #-2147483648
+; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
+; CHECK7M-NEXT: asrs r1, r1, #31
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti64i64:
; CHECK81M: @ %bb.0:
-; CHECK81M-NEXT: cmp.w r1, #-1
; CHECK81M-NEXT: mvn r0, #-2147483648
-; CHECK81M-NEXT: cinv r0, r0, le
-; CHECK81M-NEXT: csetm r1, le
+; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
+; CHECK81M-NEXT: asrs r1, r1, #31
; CHECK81M-NEXT: bx lr
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -99,9 +79,8 @@ define i64 @selecti64i64(i64 %a) {
define i32 @selecti64i32(i64 %a) {
; CHECK7A-LABEL: selecti64i32:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: mov r0, #-2147483648
-; CHECK7A-NEXT: cmn r1, #1
-; CHECK7A-NEXT: mvngt r0, #-2147483648
+; CHECK7A-NEXT: mvn r0, #-2147483648
+; CHECK7A-NEXT: eor r0, r0, r1, asr #31
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti64i32:
@@ -120,17 +99,14 @@ define i32 @selecti64i32(i64 %a) {
;
; CHECK7M-LABEL: selecti64i32:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: mov.w r0, #-2147483648
-; CHECK7M-NEXT: cmp.w r1, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: mvngt r0, #-2147483648
+; CHECK7M-NEXT: mvn r0, #-2147483648
+; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti64i32:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: mvn r0, #-2147483648
-; CHECK81M-NEXT: cmp.w r1, #-1
-; CHECK81M-NEXT: cinv r0, r0, le
+; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
; CHECK81M-NEXT: bx lr
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i32 2147483647, i32 -2147483648
@@ -140,56 +116,37 @@ define i32 @selecti64i32(i64 %a) {
define i64 @selecti32i64(i32 %a) {
; CHECK7A-LABEL: selecti32i64:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: mov r2, #-2147483648
-; CHECK7A-NEXT: cmn r0, #1
-; CHECK7A-NEXT: mvn r1, #0
-; CHECK7A-NEXT: mvngt r2, #-2147483648
-; CHECK7A-NEXT: movwgt r1, #0
+; CHECK7A-NEXT: mvn r1, #-2147483648
+; CHECK7A-NEXT: eor r2, r1, r0, asr #31
+; CHECK7A-NEXT: asr r1, r0, #31
; CHECK7A-NEXT: mov r0, r2
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti32i64:
; CHECK6M: @ %bb.0:
-; CHECK6M-NEXT: mov r2, r0
-; CHECK6M-NEXT: cmp r0, #0
-; CHECK6M-NEXT: bge .LBB3_2
-; CHECK6M-NEXT: @ %bb.1:
-; CHECK6M-NEXT: movs r0, #1
-; CHECK6M-NEXT: lsls r0, r0, #31
-; CHECK6M-NEXT: b .LBB3_3
-; CHECK6M-NEXT: .LBB3_2:
+; CHECK6M-NEXT: asrs r1, r0, #31
; CHECK6M-NEXT: ldr r0, .LCPI3_0
-; CHECK6M-NEXT: .LBB3_3:
-; CHECK6M-NEXT: movs r1, #0
-; CHECK6M-NEXT: cmp r2, #0
-; CHECK6M-NEXT: bge .LBB3_5
-; CHECK6M-NEXT: @ %bb.4:
-; CHECK6M-NEXT: mvns r1, r1
-; CHECK6M-NEXT: .LBB3_5:
+; CHECK6M-NEXT: eors r0, r1
; CHECK6M-NEXT: bx lr
; CHECK6M-NEXT: .p2align 2
-; CHECK6M-NEXT: @ %bb.6:
+; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: .LCPI3_0:
; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK7M-LABEL: selecti32i64:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: mov.w r2, #-2147483648
-; CHECK7M-NEXT: cmp.w r0, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: mvngt r2, #-2147483648
-; CHECK7M-NEXT: mov.w r1, #-1
+; CHECK7M-NEXT: mvn r1, #-2147483648
+; CHECK7M-NEXT: eor.w r2, r1, r0, asr #31
+; CHECK7M-NEXT: asrs r1, r0, #31
; CHECK7M-NEXT: mov r0, r2
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: movgt r1, #0
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti32i64:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: mvn r1, #-2147483648
-; CHECK81M-NEXT: cmp.w r0, #-1
-; CHECK81M-NEXT: cinv r0, r1, le
-; CHECK81M-NEXT: csetm r1, le
+; CHECK81M-NEXT: eor.w r2, r1, r0, asr #31
+; CHECK81M-NEXT: asrs r1, r0, #31
+; CHECK81M-NEXT: mov r0, r2
; CHECK81M-NEXT: bx lr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -232,37 +189,27 @@ define i8 @xori32i8(i32 %a) {
define i32 @selecti32i32(i32 %a) {
; CHECK7A-LABEL: selecti32i32:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: mvn r1, #84
-; CHECK7A-NEXT: cmn r0, #1
-; CHECK7A-NEXT: movwgt r1, #84
-; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: mov r1, #84
+; CHECK7A-NEXT: eor r0, r1, r0, asr #31
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti32i32:
; CHECK6M: @ %bb.0:
-; CHECK6M-NEXT: mov r1, r0
+; CHECK6M-NEXT: asrs r1, r0, #31
; CHECK6M-NEXT: movs r0, #84
-; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB5_2
-; CHECK6M-NEXT: @ %bb.1:
-; CHECK6M-NEXT: mvns r0, r0
-; CHECK6M-NEXT: .LBB5_2:
+; CHECK6M-NEXT: eors r0, r1
; CHECK6M-NEXT: bx lr
;
; CHECK7M-LABEL: selecti32i32:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: mvn r1, #84
-; CHECK7M-NEXT: cmp.w r0, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: movgt r1, #84
-; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: movs r1, #84
+; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti32i32:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: movs r1, #84
-; CHECK81M-NEXT: cmp.w r0, #-1
-; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
; CHECK81M-NEXT: bx lr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -272,37 +219,27 @@ define i32 @selecti32i32(i32 %a) {
define i8 @selecti32i8(i32 %a) {
; CHECK7A-LABEL: selecti32i8:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: mvn r1, #84
-; CHECK7A-NEXT: cmn r0, #1
-; CHECK7A-NEXT: movwgt r1, #84
-; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: mov r1, #84
+; CHECK7A-NEXT: eor r0, r1, r0, asr #31
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti32i8:
; CHECK6M: @ %bb.0:
-; CHECK6M-NEXT: mov r1, r0
+; CHECK6M-NEXT: asrs r1, r0, #31
; CHECK6M-NEXT: movs r0, #84
-; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB6_2
-; CHECK6M-NEXT: @ %bb.1:
-; CHECK6M-NEXT: mvns r0, r0
-; CHECK6M-NEXT: .LBB6_2:
+; CHECK6M-NEXT: eors r0, r1
; CHECK6M-NEXT: bx lr
;
; CHECK7M-LABEL: selecti32i8:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: mvn r1, #84
-; CHECK7M-NEXT: cmp.w r0, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: movgt r1, #84
-; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: movs r1, #84
+; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti32i8:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: movs r1, #84
-; CHECK81M-NEXT: cmp.w r0, #-1
-; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
; CHECK81M-NEXT: bx lr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i8 84, i8 -85
@@ -312,38 +249,31 @@ define i8 @selecti32i8(i32 %a) {
define i32 @selecti8i32(i8 %a) {
; CHECK7A-LABEL: selecti8i32:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: sxtb r1, r0
-; CHECK7A-NEXT: mvn r0, #84
-; CHECK7A-NEXT: cmn r1, #1
-; CHECK7A-NEXT: movwgt r0, #84
+; CHECK7A-NEXT: sxtb r0, r0
+; CHECK7A-NEXT: mov r1, #84
+; CHECK7A-NEXT: eor r0, r1, r0, asr #7
; CHECK7A-NEXT: bx lr
;
; CHECK6M-LABEL: selecti8i32:
; CHECK6M: @ %bb.0:
-; CHECK6M-NEXT: sxtb r1, r0
+; CHECK6M-NEXT: sxtb r0, r0
+; CHECK6M-NEXT: asrs r1, r0, #7
; CHECK6M-NEXT: movs r0, #84
-; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB7_2
-; CHECK6M-NEXT: @ %bb.1:
-; CHECK6M-NEXT: mvns r0, r0
-; CHECK6M-NEXT: .LBB7_2:
+; CHECK6M-NEXT: eors r0, r1
; CHECK6M-NEXT: bx lr
;
; CHECK7M-LABEL: selecti8i32:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: sxtb r1, r0
-; CHECK7M-NEXT: mvn r0, #84
-; CHECK7M-NEXT: cmp.w r1, #-1
-; CHECK7M-NEXT: it gt
-; CHECK7M-NEXT: movgt r0, #84
+; CHECK7M-NEXT: sxtb r0, r0
+; CHECK7M-NEXT: movs r1, #84
+; CHECK7M-NEXT: eor.w r0, r1, r0, asr #7
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: selecti8i32:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: sxtb r0, r0
; CHECK81M-NEXT: movs r1, #84
-; CHECK81M-NEXT: cmp.w r0, #-1
-; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: eor.w r0, r1, r0, asr #7
; CHECK81M-NEXT: bx lr
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
diff --git a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
index fb9df2fcc7d3..2dcf5792a90c 100644
--- a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
@@ -17,11 +17,9 @@ define i32 @xori64i32(i64 %a) {
define i64 @selecti64i64(i64 %a) {
; CHECK-LABEL: selecti64i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lis 4, 32767
-; CHECK-NEXT: cmpdi 3, -1
-; CHECK-NEXT: ori 3, 4, 65535
-; CHECK-NEXT: lis 4, -32768
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: sradi 3, 3, 63
+; CHECK-NEXT: xori 3, 3, 65535
+; CHECK-NEXT: xoris 3, 3, 32767
; CHECK-NEXT: blr
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -31,11 +29,9 @@ define i64 @selecti64i64(i64 %a) {
define i32 @selecti64i32(i64 %a) {
; CHECK-LABEL: selecti64i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lis 4, 32767
-; CHECK-NEXT: cmpdi 3, -1
-; CHECK-NEXT: ori 3, 4, 65535
-; CHECK-NEXT: lis 4, -32768
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: sradi 3, 3, 63
+; CHECK-NEXT: xori 3, 3, 65535
+; CHECK-NEXT: xoris 3, 3, 32767
; CHECK-NEXT: blr
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i32 2147483647, i32 -2147483648
@@ -45,11 +41,10 @@ define i32 @selecti64i32(i64 %a) {
define i64 @selecti32i64(i32 %a) {
; CHECK-LABEL: selecti32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lis 4, 32767
-; CHECK-NEXT: cmpwi 3, -1
-; CHECK-NEXT: ori 3, 4, 65535
-; CHECK-NEXT: lis 4, -32768
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: xori 3, 3, 65535
+; CHECK-NEXT: xoris 3, 3, 32767
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -73,10 +68,9 @@ define i8 @xori32i8(i32 %a) {
define i32 @selecti32i32(i32 %a) {
; CHECK-LABEL: selecti32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li 4, -85
-; CHECK-NEXT: cmpwi 3, -1
-; CHECK-NEXT: li 3, 84
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -86,10 +80,9 @@ define i32 @selecti32i32(i32 %a) {
define i8 @selecti32i8(i32 %a) {
; CHECK-LABEL: selecti32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li 4, -85
-; CHECK-NEXT: cmpwi 3, -1
-; CHECK-NEXT: li 3, 84
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i8 84, i8 -85
@@ -100,10 +93,9 @@ define i32 @selecti8i32(i8 %a) {
; CHECK-LABEL: selecti8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3
-; CHECK-NEXT: li 4, -85
-; CHECK-NEXT: cmpwi 3, -1
-; CHECK-NEXT: li 3, 84
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: srawi 3, 3, 7
+; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
index b500b71b6297..a9b26b63f2bb 100644
--- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll
+++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
@@ -27,24 +27,18 @@ define i32 @xori64i32(i64 %a) {
define i64 @selecti64i64(i64 %a) {
; CHECK32-LABEL: selecti64i64:
; CHECK32: # %bb.0:
+; CHECK32-NEXT: srai a1, a1, 31
; CHECK32-NEXT: lui a0, 524288
-; CHECK32-NEXT: bgez a1, .LBB1_2
-; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a1, zero, -1
-; CHECK32-NEXT: ret
-; CHECK32-NEXT: .LBB1_2:
-; CHECK32-NEXT: mv a1, zero
; CHECK32-NEXT: addi a0, a0, -1
+; CHECK32-NEXT: xor a0, a1, a0
; CHECK32-NEXT: ret
;
; CHECK64-LABEL: selecti64i64:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: mv a1, a0
-; CHECK64-NEXT: lui a0, 524288
-; CHECK64-NEXT: bltz a1, .LBB1_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addiw a0, a0, -1
-; CHECK64-NEXT: .LBB1_2:
+; CHECK64-NEXT: srai a0, a0, 63
+; CHECK64-NEXT: lui a1, 524288
+; CHECK64-NEXT: addiw a1, a1, -1
+; CHECK64-NEXT: xor a0, a0, a1
; CHECK64-NEXT: ret
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -62,12 +56,10 @@ define i32 @selecti64i32(i64 %a) {
;
; CHECK64-LABEL: selecti64i32:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: mv a1, a0
-; CHECK64-NEXT: lui a0, 524288
-; CHECK64-NEXT: bltz a1, .LBB2_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addiw a0, a0, -1
-; CHECK64-NEXT: .LBB2_2:
+; CHECK64-NEXT: srai a0, a0, 63
+; CHECK64-NEXT: lui a1, 524288
+; CHECK64-NEXT: addiw a1, a1, -1
+; CHECK64-NEXT: xor a0, a0, a1
; CHECK64-NEXT: ret
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i32 2147483647, i32 -2147483648
@@ -77,25 +69,18 @@ define i32 @selecti64i32(i64 %a) {
define i64 @selecti32i64(i32 %a) {
; CHECK32-LABEL: selecti32i64:
; CHECK32: # %bb.0:
-; CHECK32-NEXT: mv a1, a0
+; CHECK32-NEXT: srai a1, a0, 31
; CHECK32-NEXT: lui a0, 524288
-; CHECK32-NEXT: bgez a1, .LBB3_2
-; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a1, zero, -1
-; CHECK32-NEXT: ret
-; CHECK32-NEXT: .LBB3_2:
-; CHECK32-NEXT: mv a1, zero
; CHECK32-NEXT: addi a0, a0, -1
+; CHECK32-NEXT: xor a0, a1, a0
; CHECK32-NEXT: ret
;
; CHECK64-LABEL: selecti32i64:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: sext.w a1, a0
-; CHECK64-NEXT: lui a0, 524288
-; CHECK64-NEXT: bltz a1, .LBB3_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addiw a0, a0, -1
-; CHECK64-NEXT: .LBB3_2:
+; CHECK64-NEXT: sraiw a0, a0, 31
+; CHECK64-NEXT: lui a1, 524288
+; CHECK64-NEXT: addiw a1, a1, -1
+; CHECK64-NEXT: xor a0, a0, a1
; CHECK64-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -125,22 +110,14 @@ define i8 @xori32i8(i32 %a) {
define i32 @selecti32i32(i32 %a) {
; CHECK32-LABEL: selecti32i32:
; CHECK32: # %bb.0:
-; CHECK32-NEXT: mv a1, a0
-; CHECK32-NEXT: addi a0, zero, 84
-; CHECK32-NEXT: bgez a1, .LBB5_2
-; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a0, zero, -85
-; CHECK32-NEXT: .LBB5_2:
+; CHECK32-NEXT: srai a0, a0, 31
+; CHECK32-NEXT: xori a0, a0, 84
; CHECK32-NEXT: ret
;
; CHECK64-LABEL: selecti32i32:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: sext.w a1, a0
-; CHECK64-NEXT: addi a0, zero, 84
-; CHECK64-NEXT: bgez a1, .LBB5_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addi a0, zero, -85
-; CHECK64-NEXT: .LBB5_2:
+; CHECK64-NEXT: sraiw a0, a0, 31
+; CHECK64-NEXT: xori a0, a0, 84
; CHECK64-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -150,22 +127,14 @@ define i32 @selecti32i32(i32 %a) {
define i8 @selecti32i8(i32 %a) {
; CHECK32-LABEL: selecti32i8:
; CHECK32: # %bb.0:
-; CHECK32-NEXT: mv a1, a0
-; CHECK32-NEXT: addi a0, zero, 84
-; CHECK32-NEXT: bgez a1, .LBB6_2
-; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a0, zero, -85
-; CHECK32-NEXT: .LBB6_2:
+; CHECK32-NEXT: srai a0, a0, 31
+; CHECK32-NEXT: xori a0, a0, 84
; CHECK32-NEXT: ret
;
; CHECK64-LABEL: selecti32i8:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: sext.w a1, a0
-; CHECK64-NEXT: addi a0, zero, 84
-; CHECK64-NEXT: bgez a1, .LBB6_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addi a0, zero, -85
-; CHECK64-NEXT: .LBB6_2:
+; CHECK64-NEXT: sraiw a0, a0, 31
+; CHECK64-NEXT: xori a0, a0, 84
; CHECK64-NEXT: ret
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i8 84, i8 -85
@@ -176,23 +145,15 @@ define i32 @selecti8i32(i8 %a) {
; CHECK32-LABEL: selecti8i32:
; CHECK32: # %bb.0:
; CHECK32-NEXT: slli a0, a0, 24
-; CHECK32-NEXT: srai a1, a0, 24
-; CHECK32-NEXT: addi a0, zero, 84
-; CHECK32-NEXT: bgez a1, .LBB7_2
-; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a0, zero, -85
-; CHECK32-NEXT: .LBB7_2:
+; CHECK32-NEXT: srai a0, a0, 31
+; CHECK32-NEXT: xori a0, a0, 84
; CHECK32-NEXT: ret
;
; CHECK64-LABEL: selecti8i32:
; CHECK64: # %bb.0:
; CHECK64-NEXT: slli a0, a0, 56
-; CHECK64-NEXT: srai a1, a0, 56
-; CHECK64-NEXT: addi a0, zero, 84
-; CHECK64-NEXT: bgez a1, .LBB7_2
-; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addi a0, zero, -85
-; CHECK64-NEXT: .LBB7_2:
+; CHECK64-NEXT: srai a0, a0, 63
+; CHECK64-NEXT: xori a0, a0, 84
; CHECK64-NEXT: ret
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -252,10 +213,10 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK32-LABEL: oneusecmp:
; CHECK32: # %bb.0:
-; CHECK32-NEXT: addi a3, zero, -128
+; CHECK32-NEXT: srai a3, a0, 31
+; CHECK32-NEXT: xori a3, a3, 127
; CHECK32-NEXT: bltz a0, .LBB10_2
; CHECK32-NEXT: # %bb.1:
-; CHECK32-NEXT: addi a3, zero, 127
; CHECK32-NEXT: mv a2, a1
; CHECK32-NEXT: .LBB10_2:
; CHECK32-NEXT: add a0, a3, a2
@@ -264,10 +225,10 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK64-LABEL: oneusecmp:
; CHECK64: # %bb.0:
; CHECK64-NEXT: sext.w a3, a0
-; CHECK64-NEXT: addi a0, zero, -128
+; CHECK64-NEXT: srli a0, a3, 31
+; CHECK64-NEXT: xori a0, a0, 127
; CHECK64-NEXT: bltz a3, .LBB10_2
; CHECK64-NEXT: # %bb.1:
-; CHECK64-NEXT: addi a0, zero, 127
; CHECK64-NEXT: mv a2, a1
; CHECK64-NEXT: .LBB10_2:
; CHECK64-NEXT: addw a0, a0, a2
diff --git a/llvm/test/CodeGen/X86/pr16031.ll b/llvm/test/CodeGen/X86/pr16031.ll
index 033a10fdfb31..eb8f400969ad 100644
--- a/llvm/test/CodeGen/X86/pr16031.ll
+++ b/llvm/test/CodeGen/X86/pr16031.ll
@@ -7,15 +7,14 @@ define i64 @main(i1 %tobool1) nounwind {
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $-12, %eax
-; CHECK-NEXT: movl $-1, %edx
-; CHECK-NEXT: cmovel %edx, %eax
-; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: movl $-1, %ecx
+; CHECK-NEXT: cmovel %ecx, %eax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: addl $-1, %esi
-; CHECK-NEXT: movl $-1, %esi
-; CHECK-NEXT: adcl $-1, %esi
-; CHECK-NEXT: cmovsl %ecx, %eax
-; CHECK-NEXT: cmovsl %ecx, %edx
+; CHECK-NEXT: adcl $-1, %ecx
+; CHECK-NEXT: cmovsl %edx, %eax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/select-constant-xor.ll b/llvm/test/CodeGen/X86/select-constant-xor.ll
index 6e1ffa1a8b0a..4b45b66b7e93 100644
--- a/llvm/test/CodeGen/X86/select-constant-xor.ll
+++ b/llvm/test/CodeGen/X86/select-constant-xor.ll
@@ -18,10 +18,9 @@ define i32 @xori64i32(i64 %a) {
define i64 @selecti64i64(i64 %a) {
; CHECK-LABEL: selecti64i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: testq %rdi, %rdi
-; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
-; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000
-; CHECK-NEXT: cmovnsq %rcx, %rax
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $63, %rax
+; CHECK-NEXT: xorq $2147483647, %rax # imm = 0x7FFFFFFF
; CHECK-NEXT: retq
%c = icmp sgt i64 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -45,10 +44,9 @@ define i32 @selecti64i32(i64 %a) {
define i64 @selecti32i64(i32 %a) {
; CHECK-LABEL: selecti32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
-; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000
-; CHECK-NEXT: cmovnsq %rcx, %rax
+; CHECK-NEXT: sarl $31, %edi
+; CHECK-NEXT: movslq %edi, %rax
+; CHECK-NEXT: xorq $2147483647, %rax # imm = 0x7FFFFFFF
; CHECK-NEXT: retq
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i64 2147483647, i64 -2147483648
@@ -74,10 +72,9 @@ define i8 @xori32i8(i32 %a) {
define i32 @selecti32i32(i32 %a) {
; CHECK-LABEL: selecti32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: movl $84, %ecx
-; CHECK-NEXT: movl $-85, %eax
-; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: xorl $84, %eax
; CHECK-NEXT: retq
%c = icmp sgt i32 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -87,10 +84,9 @@ define i32 @selecti32i32(i32 %a) {
define i8 @selecti32i8(i32 %a) {
; CHECK-LABEL: selecti32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: movl $84, %ecx
-; CHECK-NEXT: movl $171, %eax
-; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: xorb $84, %al
; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = icmp sgt i32 %a, -1
@@ -101,10 +97,9 @@ define i8 @selecti32i8(i32 %a) {
define i32 @selecti8i32(i8 %a) {
; CHECK-LABEL: selecti8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $84, %ecx
-; CHECK-NEXT: movl $-85, %eax
-; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: sarb $7, %dil
+; CHECK-NEXT: movsbl %dil, %eax
+; CHECK-NEXT: xorl $84, %eax
; CHECK-NEXT: retq
%c = icmp sgt i8 %a, -1
%s = select i1 %c, i32 84, i32 -85
@@ -141,12 +136,12 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-LABEL: oneusecmp:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: xorl $127, %eax
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: cmovsl %edx, %esi
-; CHECK-NEXT: leal -128(%rsi), %ecx
-; CHECK-NEXT: leal 127(%rsi), %eax
-; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: addl %esi, %eax
; CHECK-NEXT: retq
%c = icmp sle i32 %a, -1
%s = select i1 %c, i32 -128, i32 127
diff --git a/llvm/test/CodeGen/X86/smul_fix_sat.ll b/llvm/test/CodeGen/X86/smul_fix_sat.ll
index 105c21751420..3d5fd06c10bb 100644
--- a/llvm/test/CodeGen/X86/smul_fix_sat.ll
+++ b/llvm/test/CodeGen/X86/smul_fix_sat.ll
@@ -371,26 +371,27 @@ define i64 @func5(i64 %x, i64 %y) {
; X86-NEXT: .cfi_offset %edi, -16
; X86-NEXT: .cfi_offset %ebx, -12
; X86-NEXT: .cfi_offset %ebp, -8
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl $0, (%esp)
; X86-NEXT: movl %esp, %edi
-; X86-NEXT: xorl %ebp, %ebp
-; X86-NEXT: xorl %ebx, %ebx
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: xorl %ecx, %esi
-; X86-NEXT: movl $-1, %esi
-; X86-NEXT: cmovsl %ebp, %esi
-; X86-NEXT: sets %bl
-; X86-NEXT: addl $2147483647, %ebx # imm = 0x7FFFFFFF
+; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: xorl %esi, %ebx
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: sarl $31, %ebp
+; X86-NEXT: xorl $2147483647, %ebp # imm = 0x7FFFFFFF
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl $-1, %ebx
+; X86-NEXT: cmovsl %eax, %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: pushl %ecx
+; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %edx
; X86-NEXT: .cfi_adjust_cfa_offset 4
-; X86-NEXT: pushl %eax
+; X86-NEXT: pushl %ecx
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: .cfi_adjust_cfa_offset 4
@@ -398,8 +399,8 @@ define i64 @func5(i64 %x, i64 %y) {
; X86-NEXT: addl $20, %esp
; X86-NEXT: .cfi_adjust_cfa_offset -20
; X86-NEXT: cmpl $0, (%esp)
-; X86-NEXT: cmovnel %esi, %eax
-; X86-NEXT: cmovnel %ebx, %edx
+; X86-NEXT: cmovnel %ebx, %eax
+; X86-NEXT: cmovnel %ebp, %edx
; X86-NEXT: addl $4, %esp
; X86-NEXT: .cfi_def_cfa_offset 20
; X86-NEXT: popl %esi
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