[llvm] 7801d79 - [DAG] Add tests for select_cc and setcc with constant patterns.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 5 02:17:31 PDT 2021
Author: David Green
Date: 2021-09-05T10:17:21+01:00
New Revision: 7801d7963d4fa48f738394c40477eefa1f57eb89
URL: https://github.com/llvm/llvm-project/commit/7801d7963d4fa48f738394c40477eefa1f57eb89
DIFF: https://github.com/llvm/llvm-project/commit/7801d7963d4fa48f738394c40477eefa1f57eb89.diff
LOG: [DAG] Add tests for select_cc and setcc with constant patterns.
Added:
llvm/test/CodeGen/AArch64/select-constant-xor.ll
llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
llvm/test/CodeGen/ARM/select-constant-xor.ll
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/X86/select-constant-xor.ll
Modified:
llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/select-constant-xor.ll b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
new file mode 100644
index 0000000000000..728a629b1b330
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-none-eabi %s -o - | FileCheck %s
+
+define i32 @xori64i32(i64 %a) {
+; CHECK-LABEL: xori64i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: asr x8, x0, #63
+; CHECK-NEXT: eor w0, w8, #0x7fffffff
+; CHECK-NEXT: ret
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK-LABEL: selecti64i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: mov w8, #2147483647
+; CHECK-NEXT: cinv x0, x8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK-LABEL: selecti64i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: mov w8, #2147483647
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK-LABEL: selecti32i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #2147483647
+; CHECK-NEXT: cinv x0, x8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK-LABEL: xori32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #84
+; CHECK-NEXT: eor w0, w8, w0, asr #31
+; CHECK-NEXT: ret
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK-LABEL: selecti32i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #84
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK-LABEL: selecti32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #84
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK-LABEL: selecti8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: mov w8, #84
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasreq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-1
+; CHECK-NEXT: cmp w8, w0, asr #31
+; CHECK-NEXT: csel w0, w1, w2, eq
+; CHECK-NEXT: ret
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasrne:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-1
+; CHECK-NEXT: cmp w8, w0, asr #31
+; CHECK-NEXT: csel w0, w1, w2, ne
+; CHECK-NEXT: ret
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @selecti32i32_0(i32 %a) {
+; CHECK-LABEL: selecti32i32_0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: asr w0, w0, #31
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 0, i32 -1
+ ret i32 %s
+}
+
+define i32 @selecti32i32_m1(i32 %a) {
+; CHECK-LABEL: selecti32i32_m1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mvn w8, w0
+; CHECK-NEXT: asr w0, w8, #31
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 -1, i32 0
+ ret i32 %s
+}
+
+define i32 @selecti32i32_1(i32 %a) {
+; CHECK-LABEL: selecti32i32_1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 1, i32 -2
+ ret i32 %s
+}
+
+define i32 @selecti32i32_sge(i32 %a) {
+; CHECK-LABEL: selecti32i32_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #12
+; CHECK-NEXT: cinv w0, w8, lt
+; CHECK-NEXT: ret
+ %c = icmp sge i32 %a, 0
+ %s = select i1 %c, i32 12, i32 -13
+ ret i32 %s
+}
+
+define i32 @selecti32i32_slt(i32 %a) {
+; CHECK-LABEL: selecti32i32_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #-13
+; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: ret
+ %c = icmp slt i32 %a, 0
+ %s = select i1 %c, i32 -13, i32 12
+ ret i32 %s
+}
+
+define i32 @selecti32i32_sle(i32 %a) {
+; CHECK-LABEL: selecti32i32_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #-13
+; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: ret
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -13, i32 12
+ ret i32 %s
+}
+
+define i32 @selecti32i32_sgt(i32 %a) {
+; CHECK-LABEL: selecti32i32_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #-13
+; CHECK-NEXT: cinv w0, w8, ge
+; CHECK-NEXT: ret
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -13, i32 12
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK-LABEL: oneusecmp:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov w8, #-128
+; CHECK-NEXT: cinv w8, w8, ge
+; CHECK-NEXT: csel w9, w2, w1, lt
+; CHECK-NEXT: add w0, w8, w9
+; CHECK-NEXT: ret
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
diff --git a/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
new file mode 100644
index 0000000000000..2b0c79a822e17
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1010 %s -o - | FileCheck %s
+
+define i32 @xori64i32(i64 %a) {
+; CHECK-LABEL: xori64i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK-LABEL: selecti64i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]
+; CHECK-NEXT: v_bfrev_b32_e32 v2, -2
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK-LABEL: selecti64i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]
+; CHECK-NEXT: v_bfrev_b32_e32 v2, -2
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK-LABEL: selecti32i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_bfrev_b32_e32 v1, -2
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v1, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK-LABEL: xori32i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK-LABEL: selecti32i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x54
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK-LABEL: selecti32i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x54
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK-LABEL: selecti8i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_mov_b32_e32 v1, -1
+; CHECK-NEXT: v_mov_b32_e32 v2, 0x54
+; CHECK-NEXT: v_cmp_gt_i16_sdwa vcc_lo, sext(v0), v1 src0_sel:BYTE_0 src1_sel:DWORD
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v2, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasreq:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasrne:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, -1, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK-LABEL: oneusecmp:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: v_mov_b32_e32 v3, 0xffffff80
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x7f, v3, vcc_lo
+; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
diff --git a/llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll b/llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
index 7af5478600bb9..19f5622f68fcd 100644
--- a/llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
+++ b/llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
@@ -1,12 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-; Note additional optimizations may cause this SGT to be replaced with a
-; CND* instruction.
-; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x,
-; CHECK-NEXT: -1
; Test a selectcc with i32 LHS/RHS and float True/False
define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) {
+; CHECK-LABEL: test:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; CHECK-NEXT: TEX 0 @6
+; CHECK-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; CHECK-NEXT: CF_END
+; CHECK-NEXT: PAD
+; CHECK-NEXT: Fetch clause starting at 6:
+; CHECK-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; CHECK-NEXT: ALU clause starting at 8:
+; CHECK-NEXT: MOV * T0.X, KC0[2].Z,
+; CHECK-NEXT: ALU clause starting at 9:
+; CHECK-NEXT: SETGT_INT * T0.W, T0.X, literal.x,
+; CHECK-NEXT: -1(nan), 0(0.000000e+00)
+; CHECK-NEXT: CNDE_INT T0.X, PV.W, 0.0, literal.x,
+; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45)
entry:
%0 = load i32, i32 addrspace(1)* %in
%1 = icmp sge i32 %0, 0
diff --git a/llvm/test/CodeGen/ARM/select-constant-xor.ll b/llvm/test/CodeGen/ARM/select-constant-xor.ll
new file mode 100644
index 0000000000000..77d7d8b4ec495
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/select-constant-xor.ll
@@ -0,0 +1,485 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7A
+; RUN: llc -mtriple=thumbv6m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK6M
+; RUN: llc -mtriple=thumbv7m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7M
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK81M
+
+define i32 @xori64i32(i64 %a) {
+; CHECK7A-LABEL: xori64i32:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mvn r0, #-2147483648
+; CHECK7A-NEXT: eor r0, r0, r1, asr #31
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: xori64i32:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: asrs r1, r1, #31
+; CHECK6M-NEXT: ldr r0, .LCPI0_0
+; CHECK6M-NEXT: eors r0, r1
+; CHECK6M-NEXT: bx lr
+; CHECK6M-NEXT: .p2align 2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: .LCPI0_0:
+; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK7M-LABEL: xori64i32:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: mvn r0, #-2147483648
+; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: xori64i32:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: mvn r0, #-2147483648
+; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
+; CHECK81M-NEXT: bx lr
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK7A-LABEL: selecti64i64:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: cmn r1, #1
+; CHECK7A-NEXT: mov r0, #-2147483648
+; CHECK7A-NEXT: mvn r1, #0
+; CHECK7A-NEXT: mvngt r0, #-2147483648
+; CHECK7A-NEXT: movwgt r1, #0
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti64i64:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB1_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: movs r0, #1
+; CHECK6M-NEXT: lsls r0, r0, #31
+; CHECK6M-NEXT: b .LBB1_3
+; CHECK6M-NEXT: .LBB1_2:
+; CHECK6M-NEXT: ldr r0, .LCPI1_0
+; CHECK6M-NEXT: .LBB1_3:
+; CHECK6M-NEXT: movs r2, #0
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB1_5
+; CHECK6M-NEXT: @ %bb.4:
+; CHECK6M-NEXT: mvns r2, r2
+; CHECK6M-NEXT: .LBB1_5:
+; CHECK6M-NEXT: mov r1, r2
+; CHECK6M-NEXT: bx lr
+; CHECK6M-NEXT: .p2align 2
+; CHECK6M-NEXT: @ %bb.6:
+; CHECK6M-NEXT: .LCPI1_0:
+; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK7M-LABEL: selecti64i64:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: cmp.w r1, #-1
+; CHECK7M-NEXT: mov.w r0, #-2147483648
+; CHECK7M-NEXT: mov.w r1, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: mvngt r0, #-2147483648
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: movgt r1, #0
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti64i64:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: cmp.w r1, #-1
+; CHECK81M-NEXT: mvn r0, #-2147483648
+; CHECK81M-NEXT: cinv r0, r0, le
+; CHECK81M-NEXT: csetm r1, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK7A-LABEL: selecti64i32:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mov r0, #-2147483648
+; CHECK7A-NEXT: cmn r1, #1
+; CHECK7A-NEXT: mvngt r0, #-2147483648
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti64i32:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: ldr r0, .LCPI2_0
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB2_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: adds r0, r0, #1
+; CHECK6M-NEXT: .LBB2_2:
+; CHECK6M-NEXT: bx lr
+; CHECK6M-NEXT: .p2align 2
+; CHECK6M-NEXT: @ %bb.3:
+; CHECK6M-NEXT: .LCPI2_0:
+; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK7M-LABEL: selecti64i32:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: mov.w r0, #-2147483648
+; CHECK7M-NEXT: cmp.w r1, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: mvngt r0, #-2147483648
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti64i32:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: mvn r0, #-2147483648
+; CHECK81M-NEXT: cmp.w r1, #-1
+; CHECK81M-NEXT: cinv r0, r0, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK7A-LABEL: selecti32i64:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mov r2, #-2147483648
+; CHECK7A-NEXT: cmn r0, #1
+; CHECK7A-NEXT: mvn r1, #0
+; CHECK7A-NEXT: mvngt r2, #-2147483648
+; CHECK7A-NEXT: movwgt r1, #0
+; CHECK7A-NEXT: mov r0, r2
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti32i64:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: mov r2, r0
+; CHECK6M-NEXT: cmp r0, #0
+; CHECK6M-NEXT: bge .LBB3_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: movs r0, #1
+; CHECK6M-NEXT: lsls r0, r0, #31
+; CHECK6M-NEXT: b .LBB3_3
+; CHECK6M-NEXT: .LBB3_2:
+; CHECK6M-NEXT: ldr r0, .LCPI3_0
+; CHECK6M-NEXT: .LBB3_3:
+; CHECK6M-NEXT: movs r1, #0
+; CHECK6M-NEXT: cmp r2, #0
+; CHECK6M-NEXT: bge .LBB3_5
+; CHECK6M-NEXT: @ %bb.4:
+; CHECK6M-NEXT: mvns r1, r1
+; CHECK6M-NEXT: .LBB3_5:
+; CHECK6M-NEXT: bx lr
+; CHECK6M-NEXT: .p2align 2
+; CHECK6M-NEXT: @ %bb.6:
+; CHECK6M-NEXT: .LCPI3_0:
+; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK7M-LABEL: selecti32i64:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: mov.w r2, #-2147483648
+; CHECK7M-NEXT: cmp.w r0, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: mvngt r2, #-2147483648
+; CHECK7M-NEXT: mov.w r1, #-1
+; CHECK7M-NEXT: mov r0, r2
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: movgt r1, #0
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti32i64:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: mvn r1, #-2147483648
+; CHECK81M-NEXT: cmp.w r0, #-1
+; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: csetm r1, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK7A-LABEL: xori32i8:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mov r1, #84
+; CHECK7A-NEXT: eor r0, r1, r0, asr #31
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: xori32i8:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: asrs r1, r0, #31
+; CHECK6M-NEXT: movs r0, #84
+; CHECK6M-NEXT: eors r0, r1
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: xori32i8:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: movs r1, #84
+; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: xori32i8:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: movs r1, #84
+; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
+; CHECK81M-NEXT: bx lr
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK7A-LABEL: selecti32i32:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mvn r1, #84
+; CHECK7A-NEXT: cmn r0, #1
+; CHECK7A-NEXT: movwgt r1, #84
+; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti32i32:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: mov r1, r0
+; CHECK6M-NEXT: movs r0, #84
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB5_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mvns r0, r0
+; CHECK6M-NEXT: .LBB5_2:
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: selecti32i32:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: mvn r1, #84
+; CHECK7M-NEXT: cmp.w r0, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: movgt r1, #84
+; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti32i32:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: movs r1, #84
+; CHECK81M-NEXT: cmp.w r0, #-1
+; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK7A-LABEL: selecti32i8:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mvn r1, #84
+; CHECK7A-NEXT: cmn r0, #1
+; CHECK7A-NEXT: movwgt r1, #84
+; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti32i8:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: mov r1, r0
+; CHECK6M-NEXT: movs r0, #84
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB6_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mvns r0, r0
+; CHECK6M-NEXT: .LBB6_2:
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: selecti32i8:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: mvn r1, #84
+; CHECK7M-NEXT: cmp.w r0, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: movgt r1, #84
+; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti32i8:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: movs r1, #84
+; CHECK81M-NEXT: cmp.w r0, #-1
+; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK7A-LABEL: selecti8i32:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: sxtb r1, r0
+; CHECK7A-NEXT: mvn r0, #84
+; CHECK7A-NEXT: cmn r1, #1
+; CHECK7A-NEXT: movwgt r0, #84
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: selecti8i32:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: sxtb r1, r0
+; CHECK6M-NEXT: movs r0, #84
+; CHECK6M-NEXT: cmp r1, #0
+; CHECK6M-NEXT: bge .LBB7_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mvns r0, r0
+; CHECK6M-NEXT: .LBB7_2:
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: selecti8i32:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: sxtb r1, r0
+; CHECK7M-NEXT: mvn r0, #84
+; CHECK7M-NEXT: cmp.w r1, #-1
+; CHECK7M-NEXT: it gt
+; CHECK7M-NEXT: movgt r0, #84
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: selecti8i32:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: sxtb r0, r0
+; CHECK81M-NEXT: movs r1, #84
+; CHECK81M-NEXT: cmp.w r0, #-1
+; CHECK81M-NEXT: cinv r0, r1, le
+; CHECK81M-NEXT: bx lr
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK7A-LABEL: icmpasreq:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mvn r3, #0
+; CHECK7A-NEXT: cmp r3, r0, asr #31
+; CHECK7A-NEXT: movne r1, r2
+; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: icmpasreq:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: asrs r0, r0, #31
+; CHECK6M-NEXT: adds r0, r0, #1
+; CHECK6M-NEXT: beq .LBB8_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mov r1, r2
+; CHECK6M-NEXT: .LBB8_2:
+; CHECK6M-NEXT: mov r0, r1
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: icmpasreq:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: asrs r0, r0, #31
+; CHECK7M-NEXT: adds r0, #1
+; CHECK7M-NEXT: it ne
+; CHECK7M-NEXT: movne r1, r2
+; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: icmpasreq:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: asrs r0, r0, #31
+; CHECK81M-NEXT: adds r0, #1
+; CHECK81M-NEXT: csel r0, r1, r2, eq
+; CHECK81M-NEXT: bx lr
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK7A-LABEL: icmpasrne:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: mvn r3, #0
+; CHECK7A-NEXT: cmp r3, r0, asr #31
+; CHECK7A-NEXT: moveq r1, r2
+; CHECK7A-NEXT: mov r0, r1
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: icmpasrne:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: asrs r0, r0, #31
+; CHECK6M-NEXT: adds r0, r0, #1
+; CHECK6M-NEXT: bne .LBB9_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mov r1, r2
+; CHECK6M-NEXT: .LBB9_2:
+; CHECK6M-NEXT: mov r0, r1
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: icmpasrne:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: asrs r0, r0, #31
+; CHECK7M-NEXT: adds r0, #1
+; CHECK7M-NEXT: it eq
+; CHECK7M-NEXT: moveq r1, r2
+; CHECK7M-NEXT: mov r0, r1
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: icmpasrne:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: asrs r0, r0, #31
+; CHECK81M-NEXT: adds r0, #1
+; CHECK81M-NEXT: csel r0, r1, r2, ne
+; CHECK81M-NEXT: bx lr
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK7A-LABEL: oneusecmp:
+; CHECK7A: @ %bb.0:
+; CHECK7A-NEXT: cmp r0, #0
+; CHECK7A-NEXT: mov r0, #127
+; CHECK7A-NEXT: mvnmi r0, #127
+; CHECK7A-NEXT: movmi r1, r2
+; CHECK7A-NEXT: add r0, r0, r1
+; CHECK7A-NEXT: bx lr
+;
+; CHECK6M-LABEL: oneusecmp:
+; CHECK6M: @ %bb.0:
+; CHECK6M-NEXT: cmp r0, #0
+; CHECK6M-NEXT: bmi .LBB10_2
+; CHECK6M-NEXT: @ %bb.1:
+; CHECK6M-NEXT: mov r2, r1
+; CHECK6M-NEXT: .LBB10_2:
+; CHECK6M-NEXT: movs r1, #127
+; CHECK6M-NEXT: cmp r0, #0
+; CHECK6M-NEXT: bpl .LBB10_4
+; CHECK6M-NEXT: @ %bb.3:
+; CHECK6M-NEXT: mvns r1, r1
+; CHECK6M-NEXT: .LBB10_4:
+; CHECK6M-NEXT: adds r0, r1, r2
+; CHECK6M-NEXT: bx lr
+;
+; CHECK7M-LABEL: oneusecmp:
+; CHECK7M: @ %bb.0:
+; CHECK7M-NEXT: cmp r0, #0
+; CHECK7M-NEXT: mov.w r0, #127
+; CHECK7M-NEXT: it mi
+; CHECK7M-NEXT: movmi r1, r2
+; CHECK7M-NEXT: it mi
+; CHECK7M-NEXT: mvnmi r0, #127
+; CHECK7M-NEXT: add r0, r1
+; CHECK7M-NEXT: bx lr
+;
+; CHECK81M-LABEL: oneusecmp:
+; CHECK81M: @ %bb.0:
+; CHECK81M-NEXT: cmp r0, #0
+; CHECK81M-NEXT: csel r0, r2, r1, mi
+; CHECK81M-NEXT: mov.w r1, #127
+; CHECK81M-NEXT: cinv r1, r1, mi
+; CHECK81M-NEXT: add r0, r1
+; CHECK81M-NEXT: bx lr
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
diff --git a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
new file mode 100644
index 0000000000000..dd11c522f0e02
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
@@ -0,0 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
+
+define i32 @xori64i32(i64 %a) {
+; CHECK-LABEL: xori64i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sradi 3, 3, 63
+; CHECK-NEXT: xori 3, 3, 65535
+; CHECK-NEXT: xoris 3, 3, 32767
+; CHECK-NEXT: blr
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK-LABEL: selecti64i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis 4, 32767
+; CHECK-NEXT: cmpdi 3, -1
+; CHECK-NEXT: ori 3, 4, 65535
+; CHECK-NEXT: lis 4, -32768
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK-LABEL: selecti64i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis 4, 32767
+; CHECK-NEXT: cmpdi 3, -1
+; CHECK-NEXT: ori 3, 4, 65535
+; CHECK-NEXT: lis 4, -32768
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK-LABEL: selecti32i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lis 4, 32767
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: ori 3, 4, 65535
+; CHECK-NEXT: lis 4, -32768
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK-LABEL: xori32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: xori 3, 3, 84
+; CHECK-NEXT: blr
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK-LABEL: selecti32i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li 4, -85
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: li 3, 84
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK-LABEL: selecti32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li 4, -85
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: li 3, 84
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK-LABEL: selecti8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: extsb 3, 3
+; CHECK-NEXT: li 4, -85
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: li 3, 84
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasreq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: iseleq 3, 4, 5
+; CHECK-NEXT: blr
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasrne:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srawi 3, 3, 31
+; CHECK-NEXT: cmpwi 3, -1
+; CHECK-NEXT: iseleq 3, 5, 4
+; CHECK-NEXT: blr
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK-LABEL: oneusecmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li 6, 127
+; CHECK-NEXT: cmpwi 3, 0
+; CHECK-NEXT: li 3, -128
+; CHECK-NEXT: isellt 3, 3, 6
+; CHECK-NEXT: isellt 4, 5, 4
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: blr
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
new file mode 100644
index 0000000000000..ad7a76b69c990
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
@@ -0,0 +1,286 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=CHECK32
+; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=CHECK64
+
+define i32 @xori64i32(i64 %a) {
+; CHECK32-LABEL: xori64i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: srai a0, a1, 31
+; CHECK32-NEXT: lui a1, 524288
+; CHECK32-NEXT: addi a1, a1, -1
+; CHECK32-NEXT: xor a0, a0, a1
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: xori64i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: srai a0, a0, 63
+; CHECK64-NEXT: lui a1, 524288
+; CHECK64-NEXT: addiw a1, a1, -1
+; CHECK64-NEXT: xor a0, a0, a1
+; CHECK64-NEXT: ret
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK32-LABEL: selecti64i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: lui a0, 524288
+; CHECK32-NEXT: bgez a1, .LBB1_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a1, zero, -1
+; CHECK32-NEXT: ret
+; CHECK32-NEXT: .LBB1_2:
+; CHECK32-NEXT: mv a1, zero
+; CHECK32-NEXT: addi a0, a0, -1
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti64i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: mv a1, a0
+; CHECK64-NEXT: lui a0, 524288
+; CHECK64-NEXT: bltz a1, .LBB1_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addiw a0, a0, -1
+; CHECK64-NEXT: .LBB1_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK32-LABEL: selecti64i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: addi a0, zero, -1
+; CHECK32-NEXT: slt a0, a0, a1
+; CHECK32-NEXT: lui a1, 524288
+; CHECK32-NEXT: sub a0, a1, a0
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti64i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: mv a1, a0
+; CHECK64-NEXT: lui a0, 524288
+; CHECK64-NEXT: bltz a1, .LBB2_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addiw a0, a0, -1
+; CHECK64-NEXT: .LBB2_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK32-LABEL: selecti32i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mv a1, a0
+; CHECK32-NEXT: lui a0, 524288
+; CHECK32-NEXT: bgez a1, .LBB3_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a1, zero, -1
+; CHECK32-NEXT: ret
+; CHECK32-NEXT: .LBB3_2:
+; CHECK32-NEXT: mv a1, zero
+; CHECK32-NEXT: addi a0, a0, -1
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti32i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a1, a0
+; CHECK64-NEXT: lui a0, 524288
+; CHECK64-NEXT: bltz a1, .LBB3_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addiw a0, a0, -1
+; CHECK64-NEXT: .LBB3_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK32-LABEL: xori32i8:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: srai a0, a0, 31
+; CHECK32-NEXT: xori a0, a0, 84
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: xori32i8:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sraiw a0, a0, 31
+; CHECK64-NEXT: xori a0, a0, 84
+; CHECK64-NEXT: ret
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK32-LABEL: selecti32i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mv a1, a0
+; CHECK32-NEXT: addi a0, zero, 84
+; CHECK32-NEXT: bgez a1, .LBB5_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a0, zero, -85
+; CHECK32-NEXT: .LBB5_2:
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti32i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a1, a0
+; CHECK64-NEXT: addi a0, zero, 84
+; CHECK64-NEXT: bgez a1, .LBB5_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addi a0, zero, -85
+; CHECK64-NEXT: .LBB5_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK32-LABEL: selecti32i8:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: mv a1, a0
+; CHECK32-NEXT: addi a0, zero, 84
+; CHECK32-NEXT: bgez a1, .LBB6_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a0, zero, -85
+; CHECK32-NEXT: .LBB6_2:
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti32i8:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a1, a0
+; CHECK64-NEXT: addi a0, zero, 84
+; CHECK64-NEXT: bgez a1, .LBB6_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addi a0, zero, -85
+; CHECK64-NEXT: .LBB6_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK32-LABEL: selecti8i32:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: slli a0, a0, 24
+; CHECK32-NEXT: srai a1, a0, 24
+; CHECK32-NEXT: addi a0, zero, 84
+; CHECK32-NEXT: bgez a1, .LBB7_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a0, zero, -85
+; CHECK32-NEXT: .LBB7_2:
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: selecti8i32:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: slli a0, a0, 56
+; CHECK64-NEXT: srai a1, a0, 56
+; CHECK64-NEXT: addi a0, zero, 84
+; CHECK64-NEXT: bgez a1, .LBB7_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addi a0, zero, -85
+; CHECK64-NEXT: .LBB7_2:
+; CHECK64-NEXT: ret
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK32-LABEL: icmpasreq:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: srai a3, a0, 31
+; CHECK32-NEXT: addi a4, zero, -1
+; CHECK32-NEXT: mv a0, a1
+; CHECK32-NEXT: beq a3, a4, .LBB8_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: mv a0, a2
+; CHECK32-NEXT: .LBB8_2:
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: icmpasreq:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sraiw a3, a0, 31
+; CHECK64-NEXT: addi a4, zero, -1
+; CHECK64-NEXT: mv a0, a1
+; CHECK64-NEXT: beq a3, a4, .LBB8_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: mv a0, a2
+; CHECK64-NEXT: .LBB8_2:
+; CHECK64-NEXT: ret
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK32-LABEL: icmpasrne:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: srai a3, a0, 31
+; CHECK32-NEXT: addi a4, zero, -1
+; CHECK32-NEXT: mv a0, a1
+; CHECK32-NEXT: bne a3, a4, .LBB9_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: mv a0, a2
+; CHECK32-NEXT: .LBB9_2:
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: icmpasrne:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sraiw a3, a0, 31
+; CHECK64-NEXT: addi a4, zero, -1
+; CHECK64-NEXT: mv a0, a1
+; CHECK64-NEXT: bne a3, a4, .LBB9_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: mv a0, a2
+; CHECK64-NEXT: .LBB9_2:
+; CHECK64-NEXT: ret
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK32-LABEL: oneusecmp:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: addi a3, zero, -128
+; CHECK32-NEXT: bltz a0, .LBB10_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addi a3, zero, 127
+; CHECK32-NEXT: mv a2, a1
+; CHECK32-NEXT: .LBB10_2:
+; CHECK32-NEXT: add a0, a3, a2
+; CHECK32-NEXT: ret
+;
+; CHECK64-LABEL: oneusecmp:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: sext.w a3, a0
+; CHECK64-NEXT: addi a0, zero, -128
+; CHECK64-NEXT: bltz a3, .LBB10_2
+; CHECK64-NEXT: # %bb.1:
+; CHECK64-NEXT: addi a0, zero, 127
+; CHECK64-NEXT: mv a2, a1
+; CHECK64-NEXT: .LBB10_2:
+; CHECK64-NEXT: addw a0, a0, a2
+; CHECK64-NEXT: ret
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
diff --git a/llvm/test/CodeGen/X86/select-constant-xor.ll b/llvm/test/CodeGen/X86/select-constant-xor.ll
new file mode 100644
index 0000000000000..9f76e99d5c1e4
--- /dev/null
+++ b/llvm/test/CodeGen/X86/select-constant-xor.ll
@@ -0,0 +1,158 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
+
+define i32 @xori64i32(i64 %a) {
+; CHECK-LABEL: xori64i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $63, %rax
+; CHECK-NEXT: xorl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
+ %shr4 = ashr i64 %a, 63
+ %conv5 = trunc i64 %shr4 to i32
+ %xor = xor i32 %conv5, 2147483647
+ ret i32 %xor
+}
+
+define i64 @selecti64i64(i64 %a) {
+; CHECK-LABEL: selecti64i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000
+; CHECK-NEXT: cmovnsq %rcx, %rax
+; CHECK-NEXT: retq
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+define i32 @selecti64i32(i64 %a) {
+; CHECK-LABEL: selecti64i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setns %cl
+; CHECK-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %c = icmp sgt i64 %a, -1
+ %s = select i1 %c, i32 2147483647, i32 -2147483648
+ ret i32 %s
+}
+
+define i64 @selecti32i64(i32 %a) {
+; CHECK-LABEL: selecti32i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000
+; CHECK-NEXT: cmovnsq %rcx, %rax
+; CHECK-NEXT: retq
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i64 2147483647, i64 -2147483648
+ ret i64 %s
+}
+
+
+
+define i8 @xori32i8(i32 %a) {
+; CHECK-LABEL: xori32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: xorb $84, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %shr4 = ashr i32 %a, 31
+ %conv5 = trunc i32 %shr4 to i8
+ %xor = xor i8 %conv5, 84
+ ret i8 %xor
+}
+
+define i32 @selecti32i32(i32 %a) {
+; CHECK-LABEL: selecti32i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: movl $84, %ecx
+; CHECK-NEXT: movl $-85, %eax
+; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: retq
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i8 @selecti32i8(i32 %a) {
+; CHECK-LABEL: selecti32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: movl $84, %ecx
+; CHECK-NEXT: movl $171, %eax
+; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %c = icmp sgt i32 %a, -1
+ %s = select i1 %c, i8 84, i8 -85
+ ret i8 %s
+}
+
+define i32 @selecti8i32(i8 %a) {
+; CHECK-LABEL: selecti8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testb %dil, %dil
+; CHECK-NEXT: movl $84, %ecx
+; CHECK-NEXT: movl $-85, %eax
+; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: retq
+ %c = icmp sgt i8 %a, -1
+ %s = select i1 %c, i32 84, i32 -85
+ ret i32 %s
+}
+
+define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasreq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: sarl $31, %edi
+; CHECK-NEXT: cmpl $-1, %edi
+; CHECK-NEXT: cmovnel %edx, %eax
+; CHECK-NEXT: retq
+ %sh = ashr i32 %input, 31
+ %c = icmp eq i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
+; CHECK-LABEL: icmpasrne:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: sarl $31, %edi
+; CHECK-NEXT: cmpl $-1, %edi
+; CHECK-NEXT: cmovel %edx, %eax
+; CHECK-NEXT: retq
+ %sh = ashr i32 %input, 31
+ %c = icmp ne i32 %sh, -1
+ %s = select i1 %c, i32 %a, i32 %b
+ ret i32 %s
+}
+
+define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
+; CHECK-LABEL: oneusecmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: cmovsl %edx, %esi
+; CHECK-NEXT: leal -128(%rsi), %ecx
+; CHECK-NEXT: leal 127(%rsi), %eax
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: retq
+ %c = icmp sle i32 %a, -1
+ %s = select i1 %c, i32 -128, i32 127
+ %s2 = select i1 %c, i32 %d, i32 %b
+ %x = add i32 %s, %s2
+ ret i32 %x
+}
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