[llvm] 5449d2d - [NFC] Run clang-format on llvm/lib/Trget/AVR/
Shivam Gupta via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 4 07:36:01 PDT 2021
Author: Shivam Gupta
Date: 2021-09-04T20:05:15+05:30
New Revision: 5449d2da657dc02cd299e526b905afd50294eb09
URL: https://github.com/llvm/llvm-project/commit/5449d2da657dc02cd299e526b905afd50294eb09
DIFF: https://github.com/llvm/llvm-project/commit/5449d2da657dc02cd299e526b905afd50294eb09.diff
LOG: [NFC] Run clang-format on llvm/lib/Trget/AVR/
The current inconsistency confuse contributors which coding guidlines to follow.
It would be better to have it consistent using clang-format tool.
Reviewed By: mhjacobson
Differential Revision: https://reviews.llvm.org/D109270
Added:
Modified:
llvm/lib/Target/AVR/AVR.h
llvm/lib/Target/AVR/AVR.td
llvm/lib/Target/AVR/AVRCallingConv.td
llvm/lib/Target/AVR/AVRDevices.td
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/lib/Target/AVR/AVRFrameLowering.cpp
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/AVR/AVRInstrFormats.td
llvm/lib/Target/AVR/AVRInstrInfo.cpp
llvm/lib/Target/AVR/AVRInstrInfo.h
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/lib/Target/AVR/AVRMCInstLower.cpp
llvm/lib/Target/AVR/AVRMCInstLower.h
llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
llvm/lib/Target/AVR/AVRRegisterInfo.cpp
llvm/lib/Target/AVR/AVRRegisterInfo.h
llvm/lib/Target/AVR/AVRRegisterInfo.td
llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
llvm/lib/Target/AVR/AVRSubtarget.h
llvm/lib/Target/AVR/AVRTargetMachine.cpp
llvm/lib/Target/AVR/AVRTargetMachine.h
llvm/lib/Target/AVR/AVRTargetObjectFile.cpp
llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h
llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h
index 7332307c07a37..143c339c0664e 100644
--- a/llvm/lib/Target/AVR/AVR.h
+++ b/llvm/lib/Target/AVR/AVR.h
@@ -32,8 +32,8 @@ FunctionPass *createAVRDynAllocaSRPass();
FunctionPass *createAVRBranchSelectionPass();
void initializeAVRShiftExpandPass(PassRegistry &);
-void initializeAVRExpandPseudoPass(PassRegistry&);
-void initializeAVRRelaxMemPass(PassRegistry&);
+void initializeAVRExpandPseudoPass(PassRegistry &);
+void initializeAVRRelaxMemPass(PassRegistry &);
/// Contains the AVR backend.
namespace AVR {
diff --git a/llvm/lib/Target/AVR/AVR.td b/llvm/lib/Target/AVR/AVR.td
index 53768f99df3b4..22ffc4a368ad6 100644
--- a/llvm/lib/Target/AVR/AVR.td
+++ b/llvm/lib/Target/AVR/AVR.td
@@ -45,8 +45,8 @@ include "AVRCallingConv.td"
//===---------------------------------------------------------------------===//
def AVRAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
}
//===---------------------------------------------------------------------===//
@@ -71,10 +71,9 @@ def AVRAsmParserVariant : AsmParserVariant {
//===---------------------------------------------------------------------===//
def AVR : Target {
- let InstructionSet = AVRInstrInfo;
- let AssemblyWriters = [AVRAsmWriter];
+ let InstructionSet = AVRInstrInfo;
+ let AssemblyWriters = [AVRAsmWriter];
- let AssemblyParsers = [AVRAsmParser];
+ let AssemblyParsers = [AVRAsmParser];
let AssemblyParserVariants = [AVRAsmParserVariant];
}
-
diff --git a/llvm/lib/Target/AVR/AVRCallingConv.td b/llvm/lib/Target/AVR/AVRCallingConv.td
index 65545e531a882..87874c5c50b27 100644
--- a/llvm/lib/Target/AVR/AVRCallingConv.td
+++ b/llvm/lib/Target/AVR/AVRCallingConv.td
@@ -14,9 +14,8 @@
//===----------------------------------------------------------------------===//
// Special return value calling convention for runtime functions.
-def RetCC_AVR_BUILTIN : CallingConv
-<[
- CCIfType<[i8], CCAssignToReg<[R24,R25]>>,
+def RetCC_AVR_BUILTIN : CallingConv<[
+ CCIfType<[i8], CCAssignToReg<[R24, R25]>>,
CCIfType<[i16], CCAssignToReg<[R23R22, R25R24]>>
]>;
@@ -27,8 +26,7 @@ def RetCC_AVR_BUILTIN : CallingConv
// The calling conventions are implemented in custom C++ code
// Calling convention for variadic functions.
-def ArgCC_AVR_Vararg : CallingConv
-<[
+def ArgCC_AVR_Vararg : CallingConv<[
// i16 are always passed through the stack with an alignment of 1.
CCAssignToStack<2, 1>
]>;
@@ -38,4 +36,4 @@ def ArgCC_AVR_Vararg : CallingConv
//===----------------------------------------------------------------------===//
def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
-def CSR_Interrupts : CalleeSavedRegs<(add (sequence "R%u", 31, 0))>;
+def CSR_Interrupts : CalleeSavedRegs<(add(sequence "R%u", 31, 0))>;
diff --git a/llvm/lib/Target/AVR/AVRDevices.td b/llvm/lib/Target/AVR/AVRDevices.td
index 9507aa40c3d80..e3cfdbcbc2a76 100644
--- a/llvm/lib/Target/AVR/AVRDevices.td
+++ b/llvm/lib/Target/AVR/AVRDevices.td
@@ -7,19 +7,18 @@
// In reality, avr1 (no SRAM) has one variant each of `LD` and `ST`.
// avr2 (with SRAM) adds the rest of the variants.
-
// A feature set aggregates features, grouping them. We don't want to create a
// new member in AVRSubtarget (to store a value) for each set because we do not
// care if the set is supported, only the subfeatures inside the set. We fix
// this by simply setting the same dummy member for all feature sets, which is
// then ignored.
class FeatureSet<string name, string desc, list<SubtargetFeature> i>
- : SubtargetFeature<name, "m_FeatureSetDummy", "true", desc, i>;
+ : SubtargetFeature<name, "m_FeatureSetDummy", "true", desc, i>;
// A family of microcontrollers, defining a set of supported features.
class Family<string name, list<SubtargetFeature> i>
- : FeatureSet<name, !strconcat("The device is a part of the ",
- name, " family"), i>;
+ : FeatureSet<
+ name, !strconcat("The device is a part of the ", name, " family"), i>;
// The device has SRAM, and supports the bare minimum of
// SRAM-relevant instructions.
@@ -32,122 +31,122 @@ class Family<string name, list<SubtargetFeature> i>
// `LDS Rd, K`
// `STS k, Rr`
// `PUSH`/`POP`
-def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
- "The device has random access memory">;
+def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
+ "The device has random access memory">;
// The device supports the `JMP k` and `CALL k` instructions.
-def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
- "The device supports the `JMP` and "
- "`CALL` instructions">;
-
+def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
+ "The device supports the `JMP` and "
+ "`CALL` instructions">;
// The device supports the indirect branches `IJMP` and `ICALL`.
-def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
- "true",
- "The device supports `IJMP`/`ICALL`"
- "instructions">;
+def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL", "true",
+ "The device supports `IJMP`/`ICALL`"
+ "instructions">;
// The device supports the extended indirect branches `EIJMP` and `EICALL`.
-def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
- "true", "The device supports the "
- "`EIJMP`/`EICALL` instructions">;
+def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL", "true",
+ "The device supports the "
+ "`EIJMP`/`EICALL` instructions">;
// The device supports `ADDI Rd, K`, `SUBI Rd, K`.
-def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
- "true", "Enable 16-bit register-immediate "
- "addition and subtraction instructions">;
+def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW", "true",
+ "Enable 16-bit register-immediate "
+ "addition and subtraction instructions">;
// The device has an 8-bit stack pointer (SP) register.
-def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
- "true", "The device has an 8-bit "
- "stack pointer">;
+def FeatureSmallStack
+ : SubtargetFeature<"smallstack", "m_hasSmallStack", "true",
+ "The device has an 8-bit "
+ "stack pointer">;
// The device supports the 16-bit GPR pair MOVW instruction.
-def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
- "The device supports the 16-bit MOVW "
- "instruction">;
+def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
+ "The device supports the 16-bit MOVW "
+ "instruction">;
// The device supports the `LPM` instruction, with implied destination being r0.
-def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
+def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
"The device supports the `LPM` instruction">;
// The device supports the `LPM Rd, Z[+] instruction.
-def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
- "The device supports the `LPM Rd, Z[+]` "
- "instruction">;
+def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
+ "The device supports the `LPM Rd, Z[+]` "
+ "instruction">;
// The device supports the `ELPM` instruction.
-def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
- "The device supports the ELPM instruction">;
+def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
+ "The device supports the ELPM instruction">;
// The device supports the `ELPM Rd, Z[+]` instructions.
-def FeatureELPMX : SubtargetFeature<"elpmx", "m_hasELPMX", "true",
- "The device supports the `ELPM Rd, Z[+]` "
- "instructions">;
+def FeatureELPMX : SubtargetFeature<"elpmx", "m_hasELPMX", "true",
+ "The device supports the `ELPM Rd, Z[+]` "
+ "instructions">;
// The device supports the `SPM` instruction.
-def FeatureSPM : SubtargetFeature<"spm", "m_hasSPM", "true",
+def FeatureSPM : SubtargetFeature<"spm", "m_hasSPM", "true",
"The device supports the `SPM` instruction">;
// The device supports the `SPM Z+` instruction.
-def FeatureSPMX : SubtargetFeature<"spmx", "m_hasSPMX", "true",
- "The device supports the `SPM Z+` "
- "instruction">;
+def FeatureSPMX : SubtargetFeature<"spmx", "m_hasSPMX", "true",
+ "The device supports the `SPM Z+` "
+ "instruction">;
// The device supports the `DES k` instruction.
-def FeatureDES : SubtargetFeature<"des", "m_hasDES", "true",
+def FeatureDES : SubtargetFeature<"des", "m_hasDES", "true",
"The device supports the `DES k` encryption "
"instruction">;
// The device supports the Read-Write-Modify instructions
// XCH, LAS, LAC, and LAT.
-def FeatureRMW : SubtargetFeature<"rmw", "m_supportsRMW", "true",
+def FeatureRMW : SubtargetFeature<"rmw", "m_supportsRMW", "true",
"The device supports the read-write-modify "
"instructions: XCH, LAS, LAC, LAT">;
// The device supports the `[F]MUL[S][U]` family of instructions.
-def FeatureMultiplication : SubtargetFeature<"mul", "m_supportsMultiplication",
- "true", "The device supports the "
- "multiplication instructions">;
+def FeatureMultiplication
+ : SubtargetFeature<"mul", "m_supportsMultiplication", "true",
+ "The device supports the "
+ "multiplication instructions">;
// The device supports the `BREAK` instruction.
-def FeatureBREAK : SubtargetFeature<"break", "m_hasBREAK", "true",
- "The device supports the `BREAK` debugging "
- "instruction">;
+def FeatureBREAK : SubtargetFeature<"break", "m_hasBREAK", "true",
+ "The device supports the `BREAK` debugging "
+ "instruction">;
// The device has instruction encodings specific to the Tiny core.
-def FeatureTinyEncoding : SubtargetFeature<"tinyencoding",
- "m_hasTinyEncoding", "true",
- "The device has Tiny core specific "
- "instruction encodings">;
+def FeatureTinyEncoding
+ : SubtargetFeature<"tinyencoding", "m_hasTinyEncoding", "true",
+ "The device has Tiny core specific "
+ "instruction encodings">;
// The device has CPU registers mapped in data address space
-def FeatureMMR : SubtargetFeature<"memmappedregs", "m_hasMemMappedGPR",
- "true", "The device has CPU registers "
+def FeatureMMR : SubtargetFeature<"memmappedregs", "m_hasMemMappedGPR", "true",
+ "The device has CPU registers "
"mapped in data address space">;
-class ELFArch<string name> : SubtargetFeature<"", "ELFArch",
- !strconcat("ELF::",name), "">;
+class ELFArch<string name>
+ : SubtargetFeature<"", "ELFArch", !strconcat("ELF::", name), "">;
// ELF e_flags architecture values
-def ELFArchAVR1 : ELFArch<"EF_AVR_ARCH_AVR1">;
-def ELFArchAVR2 : ELFArch<"EF_AVR_ARCH_AVR2">;
-def ELFArchAVR25 : ELFArch<"EF_AVR_ARCH_AVR25">;
-def ELFArchAVR3 : ELFArch<"EF_AVR_ARCH_AVR3">;
-def ELFArchAVR31 : ELFArch<"EF_AVR_ARCH_AVR31">;
-def ELFArchAVR35 : ELFArch<"EF_AVR_ARCH_AVR35">;
-def ELFArchAVR4 : ELFArch<"EF_AVR_ARCH_AVR4">;
-def ELFArchAVR5 : ELFArch<"EF_AVR_ARCH_AVR5">;
-def ELFArchAVR51 : ELFArch<"EF_AVR_ARCH_AVR51">;
-def ELFArchAVR6 : ELFArch<"EF_AVR_ARCH_AVR6">;
-def ELFArchTiny : ELFArch<"EF_AVR_ARCH_AVRTINY">;
-def ELFArchXMEGA1 : ELFArch<"EF_AVR_ARCH_XMEGA1">;
-def ELFArchXMEGA2 : ELFArch<"EF_AVR_ARCH_XMEGA2">;
-def ELFArchXMEGA3 : ELFArch<"EF_AVR_ARCH_XMEGA3">;
-def ELFArchXMEGA4 : ELFArch<"EF_AVR_ARCH_XMEGA4">;
-def ELFArchXMEGA5 : ELFArch<"EF_AVR_ARCH_XMEGA5">;
-def ELFArchXMEGA6 : ELFArch<"EF_AVR_ARCH_XMEGA6">;
-def ELFArchXMEGA7 : ELFArch<"EF_AVR_ARCH_XMEGA7">;
+def ELFArchAVR1 : ELFArch<"EF_AVR_ARCH_AVR1">;
+def ELFArchAVR2 : ELFArch<"EF_AVR_ARCH_AVR2">;
+def ELFArchAVR25 : ELFArch<"EF_AVR_ARCH_AVR25">;
+def ELFArchAVR3 : ELFArch<"EF_AVR_ARCH_AVR3">;
+def ELFArchAVR31 : ELFArch<"EF_AVR_ARCH_AVR31">;
+def ELFArchAVR35 : ELFArch<"EF_AVR_ARCH_AVR35">;
+def ELFArchAVR4 : ELFArch<"EF_AVR_ARCH_AVR4">;
+def ELFArchAVR5 : ELFArch<"EF_AVR_ARCH_AVR5">;
+def ELFArchAVR51 : ELFArch<"EF_AVR_ARCH_AVR51">;
+def ELFArchAVR6 : ELFArch<"EF_AVR_ARCH_AVR6">;
+def ELFArchTiny : ELFArch<"EF_AVR_ARCH_AVRTINY">;
+def ELFArchXMEGA1 : ELFArch<"EF_AVR_ARCH_XMEGA1">;
+def ELFArchXMEGA2 : ELFArch<"EF_AVR_ARCH_XMEGA2">;
+def ELFArchXMEGA3 : ELFArch<"EF_AVR_ARCH_XMEGA3">;
+def ELFArchXMEGA4 : ELFArch<"EF_AVR_ARCH_XMEGA4">;
+def ELFArchXMEGA5 : ELFArch<"EF_AVR_ARCH_XMEGA5">;
+def ELFArchXMEGA6 : ELFArch<"EF_AVR_ARCH_XMEGA6">;
+def ELFArchXMEGA7 : ELFArch<"EF_AVR_ARCH_XMEGA7">;
//===---------------------------------------------------------------------===//
// AVR Families
@@ -155,68 +154,64 @@ def ELFArchXMEGA7 : ELFArch<"EF_AVR_ARCH_XMEGA7">;
// The device has at least the bare minimum that **every** single AVR
// device should have.
-def FamilyAVR0 : Family<"avr0", []>;
+def FamilyAVR0 : Family<"avr0", []>;
-def FamilyAVR1 : Family<"avr1", [FamilyAVR0, FeatureLPM, FeatureMMR]>;
+def FamilyAVR1 : Family<"avr1", [FamilyAVR0, FeatureLPM, FeatureMMR]>;
-def FamilyAVR2 : Family<"avr2",
- [FamilyAVR1, FeatureIJMPCALL, FeatureADDSUBIW,
- FeatureSRAM]>;
+def FamilyAVR2
+ : Family<"avr2",
+ [FamilyAVR1, FeatureIJMPCALL, FeatureADDSUBIW, FeatureSRAM]>;
-def FamilyAVR25 : Family<"avr25",
- [FamilyAVR2, FeatureMOVW, FeatureLPMX,
- FeatureSPM, FeatureBREAK]>;
+def FamilyAVR25
+ : Family<"avr25",
+ [FamilyAVR2, FeatureMOVW, FeatureLPMX, FeatureSPM, FeatureBREAK]>;
-def FamilyAVR3 : Family<"avr3",
- [FamilyAVR2, FeatureJMPCALL]>;
+def FamilyAVR3 : Family<"avr3", [FamilyAVR2, FeatureJMPCALL]>;
-def FamilyAVR31 : Family<"avr31",
- [FamilyAVR3, FeatureELPM]>;
+def FamilyAVR31 : Family<"avr31", [FamilyAVR3, FeatureELPM]>;
-def FamilyAVR35 : Family<"avr35",
- [FamilyAVR3, FeatureMOVW, FeatureLPMX,
- FeatureSPM, FeatureBREAK]>;
+def FamilyAVR35
+ : Family<"avr35",
+ [FamilyAVR3, FeatureMOVW, FeatureLPMX, FeatureSPM, FeatureBREAK]>;
-def FamilyAVR4 : Family<"avr4",
- [FamilyAVR2, FeatureMultiplication,
- FeatureMOVW, FeatureLPMX, FeatureSPM,
- FeatureBREAK]>;
+def FamilyAVR4 : Family<"avr4", [
+ FamilyAVR2, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
+ FeatureBREAK
+]>;
-def FamilyAVR5 : Family<"avr5",
- [FamilyAVR3, FeatureMultiplication,
- FeatureMOVW, FeatureLPMX, FeatureSPM,
- FeatureBREAK]>;
+def FamilyAVR5 : Family<"avr5", [
+ FamilyAVR3, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
+ FeatureBREAK
+]>;
-def FamilyAVR51 : Family<"avr51",
- [FamilyAVR5, FeatureELPM, FeatureELPMX]>;
+def FamilyAVR51 : Family<"avr51", [FamilyAVR5, FeatureELPM, FeatureELPMX]>;
-def FamilyAVR6 : Family<"avr6",
- [FamilyAVR51]>;
+def FamilyAVR6 : Family<"avr6", [FamilyAVR51]>;
-def FamilyTiny : Family<"avrtiny",
- [FamilyAVR0, FeatureBREAK, FeatureSRAM,
- FeatureTinyEncoding]>;
+def FamilyTiny
+ : Family<"avrtiny",
+ [FamilyAVR0, FeatureBREAK, FeatureSRAM, FeatureTinyEncoding]>;
-def FamilyXMEGA : Family<"xmega",
- [FamilyAVR0, FeatureLPM, FeatureIJMPCALL, FeatureADDSUBIW,
- FeatureSRAM, FeatureJMPCALL, FeatureMultiplication,
- FeatureMOVW, FeatureLPMX, FeatureSPM,
- FeatureBREAK, FeatureEIJMPCALL, FeatureSPMX,
- FeatureDES, FeatureELPM, FeatureELPMX]>;
+def FamilyXMEGA : Family<"xmega", [
+ FamilyAVR0, FeatureLPM, FeatureIJMPCALL, FeatureADDSUBIW, FeatureSRAM,
+ FeatureJMPCALL, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
+ FeatureBREAK, FeatureEIJMPCALL, FeatureSPMX, FeatureDES, FeatureELPM,
+ FeatureELPMX
+]>;
-def FamilyXMEGAU : Family<"xmegau",
- [FamilyXMEGA, FeatureRMW]>;
+def FamilyXMEGAU : Family<"xmegau", [FamilyXMEGA, FeatureRMW]>;
-def FeatureSetSpecial : FeatureSet<"special",
- "Enable use of the entire instruction "
- "set - used for debugging",
- [FeatureSRAM, FeatureJMPCALL,
- FeatureIJMPCALL, FeatureEIJMPCALL,
- FeatureADDSUBIW, FeatureMOVW,
- FeatureLPM, FeatureLPMX, FeatureELPM,
- FeatureELPMX, FeatureSPM, FeatureSPMX,
- FeatureDES, FeatureRMW,
- FeatureMultiplication, FeatureBREAK, FeatureMMR]>;
+def FeatureSetSpecial
+ : FeatureSet<"special",
+ "Enable use of the entire instruction "
+ "set - used for debugging",
+ [
+ FeatureSRAM, FeatureJMPCALL, FeatureIJMPCALL,
+ FeatureEIJMPCALL, FeatureADDSUBIW, FeatureMOVW, FeatureLPM,
+ FeatureLPMX, FeatureELPM, FeatureELPMX, FeatureSPM,
+ FeatureSPMX, FeatureDES, FeatureRMW, FeatureMultiplication,
+ FeatureBREAK, FeatureMMR
+ ]>;
//===---------------------------------------------------------------------===//
// AVR microcontrollers supported.
@@ -224,284 +219,282 @@ def FeatureSetSpecial : FeatureSet<"special",
class Device<string Name, Family Fam, ELFArch Arch,
list<SubtargetFeature> ExtraFeatures = []>
- : Processor<Name, NoItineraries, !listconcat([Fam,Arch],ExtraFeatures)>;
+ : Processor<Name, NoItineraries, !listconcat([Fam, Arch], ExtraFeatures)>;
// Generic MCUs
// Note that several versions of GCC has strange ELF architecture
// settings for backwards compatibility - see `gas/config/tc-avr.c`
// in AVR binutils. We do not replicate this.
-def : Device<"avr1", FamilyAVR1, ELFArchAVR1>;
-def : Device<"avr2", FamilyAVR2, ELFArchAVR2>;
-def : Device<"avr25", FamilyAVR25, ELFArchAVR25>;
-def : Device<"avr3", FamilyAVR3, ELFArchAVR3>;
-def : Device<"avr31", FamilyAVR31, ELFArchAVR31>;
-def : Device<"avr35", FamilyAVR35, ELFArchAVR35>;
-def : Device<"avr4", FamilyAVR4, ELFArchAVR4>;
-def : Device<"avr5", FamilyAVR5, ELFArchAVR5>;
-def : Device<"avr51", FamilyAVR51, ELFArchAVR51>;
-def : Device<"avr6", FamilyAVR6, ELFArchAVR6>;
-def : Device<"avrxmega1", FamilyXMEGA, ELFArchXMEGA1>;
-def : Device<"avrxmega2", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"avrxmega3", FamilyXMEGA, ELFArchXMEGA3>;
-def : Device<"avrxmega4", FamilyXMEGA, ELFArchXMEGA4>;
-def : Device<"avrxmega5", FamilyXMEGA, ELFArchXMEGA5>;
-def : Device<"avrxmega6", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"avrxmega7", FamilyXMEGA, ELFArchXMEGA7>;
-def : Device<"avrtiny", FamilyTiny, ELFArchTiny>;
+def : Device<"avr1", FamilyAVR1, ELFArchAVR1>;
+def : Device<"avr2", FamilyAVR2, ELFArchAVR2>;
+def : Device<"avr25", FamilyAVR25, ELFArchAVR25>;
+def : Device<"avr3", FamilyAVR3, ELFArchAVR3>;
+def : Device<"avr31", FamilyAVR31, ELFArchAVR31>;
+def : Device<"avr35", FamilyAVR35, ELFArchAVR35>;
+def : Device<"avr4", FamilyAVR4, ELFArchAVR4>;
+def : Device<"avr5", FamilyAVR5, ELFArchAVR5>;
+def : Device<"avr51", FamilyAVR51, ELFArchAVR51>;
+def : Device<"avr6", FamilyAVR6, ELFArchAVR6>;
+def : Device<"avrxmega1", FamilyXMEGA, ELFArchXMEGA1>;
+def : Device<"avrxmega2", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"avrxmega3", FamilyXMEGA, ELFArchXMEGA3>;
+def : Device<"avrxmega4", FamilyXMEGA, ELFArchXMEGA4>;
+def : Device<"avrxmega5", FamilyXMEGA, ELFArchXMEGA5>;
+def : Device<"avrxmega6", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"avrxmega7", FamilyXMEGA, ELFArchXMEGA7>;
+def : Device<"avrtiny", FamilyTiny, ELFArchTiny>;
// Specific MCUs
-def : Device<"at90s1200", FamilyAVR0, ELFArchAVR1>;
-def : Device<"attiny11", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny12", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny15", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny28", FamilyAVR1, ELFArchAVR1>;
-def : Device<"at90s2313", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2323", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2333", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2343", FamilyAVR2, ELFArchAVR2>;
-def : Device<"attiny22", FamilyAVR2, ELFArchAVR2>;
-def : Device<"attiny26", FamilyAVR2, ELFArchAVR2, [FeatureLPMX]>;
-def : Device<"at86rf401", FamilyAVR2, ELFArchAVR25,
- [FeatureMOVW, FeatureLPMX]>;
-def : Device<"at90s4414", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s4433", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s4434", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s8515", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90c8534", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s8535", FamilyAVR2, ELFArchAVR2>;
-def : Device<"ata5272", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny13", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny13a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny2313", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny2313a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny24", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny24a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny4313", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny44", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny44a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny84", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny84a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny25", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny45", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny85", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny261", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny261a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny441", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny461", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny461a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny841", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny861", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny861a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny87", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny43u", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny48", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny88", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny828", FamilyAVR25, ELFArchAVR25>;
-def : Device<"at43usb355", FamilyAVR3, ELFArchAVR3>;
-def : Device<"at76c711", FamilyAVR3, ELFArchAVR3>;
-def : Device<"atmega103", FamilyAVR31, ELFArchAVR31>;
-def : Device<"at43usb320", FamilyAVR31, ELFArchAVR31>;
-def : Device<"attiny167", FamilyAVR35, ELFArchAVR35>;
-def : Device<"at90usb82", FamilyAVR35, ELFArchAVR35>;
-def : Device<"at90usb162", FamilyAVR35, ELFArchAVR35>;
-def : Device<"ata5505", FamilyAVR35, ELFArchAVR35>;
-def : Device<"atmega8u2", FamilyAVR35, ELFArchAVR35>;
-def : Device<"atmega16u2", FamilyAVR35, ELFArchAVR35>;
-def : Device<"atmega32u2", FamilyAVR35, ELFArchAVR35>;
-def : Device<"attiny1634", FamilyAVR35, ELFArchAVR35>;
-def : Device<"atmega8", FamilyAVR2, ELFArchAVR4,
+def : Device<"at90s1200", FamilyAVR0, ELFArchAVR1>;
+def : Device<"attiny11", FamilyAVR1, ELFArchAVR1>;
+def : Device<"attiny12", FamilyAVR1, ELFArchAVR1>;
+def : Device<"attiny15", FamilyAVR1, ELFArchAVR1>;
+def : Device<"attiny28", FamilyAVR1, ELFArchAVR1>;
+def : Device<"at90s2313", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s2323", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s2333", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s2343", FamilyAVR2, ELFArchAVR2>;
+def : Device<"attiny22", FamilyAVR2, ELFArchAVR2>;
+def : Device<"attiny26", FamilyAVR2, ELFArchAVR2, [FeatureLPMX]>;
+def : Device<"at86rf401", FamilyAVR2, ELFArchAVR25, [FeatureMOVW, FeatureLPMX]>;
+def : Device<"at90s4414", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s4433", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s4434", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s8515", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90c8534", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s8535", FamilyAVR2, ELFArchAVR2>;
+def : Device<"ata5272", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny13", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny13a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny2313", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny2313a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny24", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny24a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny4313", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny44", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny44a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny84", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny84a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny25", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny45", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny85", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny261", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny261a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny441", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny461", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny461a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny841", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny861", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny861a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny87", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny43u", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny48", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny88", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny828", FamilyAVR25, ELFArchAVR25>;
+def : Device<"at43usb355", FamilyAVR3, ELFArchAVR3>;
+def : Device<"at76c711", FamilyAVR3, ELFArchAVR3>;
+def : Device<"atmega103", FamilyAVR31, ELFArchAVR31>;
+def : Device<"at43usb320", FamilyAVR31, ELFArchAVR31>;
+def : Device<"attiny167", FamilyAVR35, ELFArchAVR35>;
+def : Device<"at90usb82", FamilyAVR35, ELFArchAVR35>;
+def : Device<"at90usb162", FamilyAVR35, ELFArchAVR35>;
+def : Device<"ata5505", FamilyAVR35, ELFArchAVR35>;
+def : Device<"atmega8u2", FamilyAVR35, ELFArchAVR35>;
+def : Device<"atmega16u2", FamilyAVR35, ELFArchAVR35>;
+def : Device<"atmega32u2", FamilyAVR35, ELFArchAVR35>;
+def : Device<"attiny1634", FamilyAVR35, ELFArchAVR35>;
+def : Device<"atmega8", FamilyAVR2, ELFArchAVR4,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"ata6289", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega8a", FamilyAVR2, ELFArchAVR4,
+def : Device<"ata6289", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega8a", FamilyAVR2, ELFArchAVR4,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"ata6285", FamilyAVR4, ELFArchAVR4>;
-def : Device<"ata6286", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega48", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega48a", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega48pa", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega48pb", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega48p", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega88", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega88a", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega88p", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega88pa", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega88pb", FamilyAVR4, ELFArchAVR4>;
-def : Device<"atmega8515", FamilyAVR2, ELFArchAVR4,
+def : Device<"ata6285", FamilyAVR4, ELFArchAVR4>;
+def : Device<"ata6286", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega48", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega48a", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega48pa", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega48pb", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega48p", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega88", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega88a", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega88p", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega88pa", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega88pb", FamilyAVR4, ELFArchAVR4>;
+def : Device<"atmega8515", FamilyAVR2, ELFArchAVR4,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"atmega8535", FamilyAVR2, ELFArchAVR4,
+def : Device<"atmega8535", FamilyAVR2, ELFArchAVR4,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"atmega8hva", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm1", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm2", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm2b", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm3", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm3b", FamilyAVR4, ELFArchAVR4>;
-def : Device<"at90pwm81", FamilyAVR4, ELFArchAVR4>;
-def : Device<"ata5790", FamilyAVR5, ELFArchAVR5>;
-def : Device<"ata5795", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega161", FamilyAVR3, ELFArchAVR5,
+def : Device<"atmega8hva", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm1", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm2", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm2b", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm3", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm3b", FamilyAVR4, ELFArchAVR4>;
+def : Device<"at90pwm81", FamilyAVR4, ELFArchAVR4>;
+def : Device<"ata5790", FamilyAVR5, ELFArchAVR5>;
+def : Device<"ata5795", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega161", FamilyAVR3, ELFArchAVR5,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"atmega162", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega163", FamilyAVR3, ELFArchAVR5,
+def : Device<"atmega162", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega163", FamilyAVR3, ELFArchAVR5,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM]>;
-def : Device<"atmega164a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega164p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega164pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega165", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega165a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega165p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega165pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega168", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega168a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega168p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega168pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega168pb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega169", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega169a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega169p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega169pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega323", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega324a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega324p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega324pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega324pb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega325", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega325a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega325p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega325pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3250", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3250a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3250p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3250pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega328", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega328p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega328pb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega329", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega329a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega329p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega329pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3290", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3290a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3290p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega3290pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega406", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega640", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega644", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega644a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega644p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega644pa", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega645", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega645a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega645p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega649", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega649a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega649p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6450", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6450a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6450p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6490", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6490a", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega6490p", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64rfr2", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega644rfr2", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16hva", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16hva2", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16hvb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16hvbrevb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32hvb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32hvbrevb", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64hve", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90can32", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90can64", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90pwm161", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90pwm216", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90pwm316", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32c1", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64c1", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16m1", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32m1", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega64m1", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega16u4", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32u4", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega32u6", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90usb646", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90usb647", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at90scr100", FamilyAVR5, ELFArchAVR5>;
-def : Device<"at94k", FamilyAVR3, ELFArchAVR5,
+def : Device<"atmega164a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega164p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega164pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega165", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega165a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega165p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega165pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega168", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega168a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega168p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega168pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega168pb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega169", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega169a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega169p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega169pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega323", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega324a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega324p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega324pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega324pb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega325", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega325a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega325p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega325pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3250", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3250a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3250p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3250pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega328", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega328p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega328pb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega329", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega329a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega329p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega329pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3290", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3290a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3290p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega3290pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega406", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega640", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega644", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega644a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega644p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega644pa", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega645", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega645a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega645p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega649", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega649a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega649p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6450", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6450a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6450p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6490", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6490a", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega6490p", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64rfr2", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega644rfr2", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16hva", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16hva2", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16hvb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16hvbrevb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32hvb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32hvbrevb", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64hve", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90can32", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90can64", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90pwm161", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90pwm216", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90pwm316", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32c1", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64c1", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16m1", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32m1", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega64m1", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega16u4", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32u4", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega32u6", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90usb646", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90usb647", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at90scr100", FamilyAVR5, ELFArchAVR5>;
+def : Device<"at94k", FamilyAVR3, ELFArchAVR5,
[FeatureMultiplication, FeatureMOVW, FeatureLPMX]>;
-def : Device<"m3000", FamilyAVR5, ELFArchAVR5>;
-def : Device<"atmega128", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega128a", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega1280", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega1281", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega1284", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega1284p", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega128rfa1", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega128rfr2", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega1284rfr2", FamilyAVR51, ELFArchAVR51>;
-def : Device<"at90can128", FamilyAVR51, ELFArchAVR51>;
-def : Device<"at90usb1286", FamilyAVR51, ELFArchAVR51>;
-def : Device<"at90usb1287", FamilyAVR51, ELFArchAVR51>;
-def : Device<"atmega2560", FamilyAVR6, ELFArchAVR6>;
-def : Device<"atmega2561", FamilyAVR6, ELFArchAVR6>;
-def : Device<"atmega256rfr2", FamilyAVR6, ELFArchAVR6>;
-def : Device<"atmega2564rfr2", FamilyAVR6, ELFArchAVR6>;
-def : Device<"atxmega16a4", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"atxmega16a4u", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega16c4", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega16d4", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"atxmega32a4", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"atxmega32a4u", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega32c4", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega32d4", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"atxmega32e5", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega16e5", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega8e5", FamilyXMEGAU, ELFArchXMEGA2>;
-def : Device<"atxmega32x1", FamilyXMEGA, ELFArchXMEGA2>;
-def : Device<"atxmega64a3", FamilyXMEGA, ELFArchXMEGA4>;
-def : Device<"atxmega64a3u", FamilyXMEGAU, ELFArchXMEGA4>;
-def : Device<"atxmega64a4u", FamilyXMEGAU, ELFArchXMEGA4>;
-def : Device<"atxmega64b1", FamilyXMEGAU, ELFArchXMEGA4>;
-def : Device<"atxmega64b3", FamilyXMEGAU, ELFArchXMEGA4>;
-def : Device<"atxmega64c3", FamilyXMEGAU, ELFArchXMEGA4>;
-def : Device<"atxmega64d3", FamilyXMEGA, ELFArchXMEGA4>;
-def : Device<"atxmega64d4", FamilyXMEGA, ELFArchXMEGA4>;
-def : Device<"atxmega64a1", FamilyXMEGA, ELFArchXMEGA5>;
-def : Device<"atxmega64a1u", FamilyXMEGAU, ELFArchXMEGA5>;
-def : Device<"atxmega128a3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega128a3u", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega128b1", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega128b3", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega128c3", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega128d3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega128d4", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega192a3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega192a3u", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega192c3", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega192d3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega256a3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega256a3u", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega256a3b", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega256a3bu", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega256c3", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega256d3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega384c3", FamilyXMEGAU, ELFArchXMEGA6>;
-def : Device<"atxmega384d3", FamilyXMEGA, ELFArchXMEGA6>;
-def : Device<"atxmega128a1", FamilyXMEGA, ELFArchXMEGA7>;
-def : Device<"atxmega128a1u", FamilyXMEGAU, ELFArchXMEGA7>;
-def : Device<"atxmega128a4u", FamilyXMEGAU, ELFArchXMEGA7>;
-def : Device<"attiny4", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny5", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny9", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny10", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny20", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny40", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny102", FamilyTiny, ELFArchTiny>;
-def : Device<"attiny104", FamilyTiny, ELFArchTiny>;
-
+def : Device<"m3000", FamilyAVR5, ELFArchAVR5>;
+def : Device<"atmega128", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega128a", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega1280", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega1281", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega1284", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega1284p", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega128rfa1", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega128rfr2", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega1284rfr2", FamilyAVR51, ELFArchAVR51>;
+def : Device<"at90can128", FamilyAVR51, ELFArchAVR51>;
+def : Device<"at90usb1286", FamilyAVR51, ELFArchAVR51>;
+def : Device<"at90usb1287", FamilyAVR51, ELFArchAVR51>;
+def : Device<"atmega2560", FamilyAVR6, ELFArchAVR6>;
+def : Device<"atmega2561", FamilyAVR6, ELFArchAVR6>;
+def : Device<"atmega256rfr2", FamilyAVR6, ELFArchAVR6>;
+def : Device<"atmega2564rfr2", FamilyAVR6, ELFArchAVR6>;
+def : Device<"atxmega16a4", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"atxmega16a4u", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega16c4", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega16d4", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"atxmega32a4", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"atxmega32a4u", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega32c4", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega32d4", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"atxmega32e5", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega16e5", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega8e5", FamilyXMEGAU, ELFArchXMEGA2>;
+def : Device<"atxmega32x1", FamilyXMEGA, ELFArchXMEGA2>;
+def : Device<"atxmega64a3", FamilyXMEGA, ELFArchXMEGA4>;
+def : Device<"atxmega64a3u", FamilyXMEGAU, ELFArchXMEGA4>;
+def : Device<"atxmega64a4u", FamilyXMEGAU, ELFArchXMEGA4>;
+def : Device<"atxmega64b1", FamilyXMEGAU, ELFArchXMEGA4>;
+def : Device<"atxmega64b3", FamilyXMEGAU, ELFArchXMEGA4>;
+def : Device<"atxmega64c3", FamilyXMEGAU, ELFArchXMEGA4>;
+def : Device<"atxmega64d3", FamilyXMEGA, ELFArchXMEGA4>;
+def : Device<"atxmega64d4", FamilyXMEGA, ELFArchXMEGA4>;
+def : Device<"atxmega64a1", FamilyXMEGA, ELFArchXMEGA5>;
+def : Device<"atxmega64a1u", FamilyXMEGAU, ELFArchXMEGA5>;
+def : Device<"atxmega128a3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega128a3u", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega128b1", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega128b3", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega128c3", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega128d3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega128d4", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega192a3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega192a3u", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega192c3", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega192d3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega256a3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega256a3u", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega256a3b", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega256a3bu", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega256c3", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega256d3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega384c3", FamilyXMEGAU, ELFArchXMEGA6>;
+def : Device<"atxmega384d3", FamilyXMEGA, ELFArchXMEGA6>;
+def : Device<"atxmega128a1", FamilyXMEGA, ELFArchXMEGA7>;
+def : Device<"atxmega128a1u", FamilyXMEGAU, ELFArchXMEGA7>;
+def : Device<"atxmega128a4u", FamilyXMEGAU, ELFArchXMEGA7>;
+def : Device<"attiny4", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny5", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny9", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny10", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny20", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny40", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny102", FamilyTiny, ELFArchTiny>;
+def : Device<"attiny104", FamilyTiny, ELFArchTiny>;
diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index f9f91f50c9d58..cb85d73772c55 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -70,25 +70,24 @@ class AVRExpandPseudo : public MachineFunctionPass {
return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
}
- MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
+ MachineRegisterInfo &getRegInfo(Block &MBB) {
+ return MBB.getParent()->getRegInfo();
+ }
bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
- template<typename Func>
- bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
+ template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
- template<typename Func>
+ template <typename Func>
bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
- bool expandAtomicArithmeticOp(unsigned MemOpcode,
- unsigned ArithOpcode,
- Block &MBB,
- BlockIt MBBI);
+ bool expandAtomicArithmeticOp(unsigned MemOpcode, unsigned ArithOpcode,
+ Block &MBB, BlockIt MBBI);
/// Specific shift implementation.
bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
@@ -150,8 +149,8 @@ bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-bool AVRExpandPseudo::
-expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
+ BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
@@ -164,14 +163,15 @@ expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(DstIsKill))
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(DstIsKill))
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
if (ImpIsDead)
MIBHI->getOperand(3).setIsDead();
@@ -183,8 +183,7 @@ expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
return true;
}
-bool AVRExpandPseudo::
-expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
@@ -196,18 +195,20 @@ expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, Op)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ auto MIBLO =
+ buildMI(MBB, MBBI, Op)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(DstIsKill))
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
// SREG is always implicitly dead
MIBLO->getOperand(3).setIsDead();
- auto MIBHI = buildMI(MBB, MBBI, Op)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ auto MIBHI =
+ buildMI(MBB, MBBI, Op)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(DstIsKill))
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
if (ImpIsDead)
MIBHI->getOperand(3).setIsDead();
@@ -216,8 +217,8 @@ expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
return true;
}
-bool AVRExpandPseudo::
- isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
+bool AVRExpandPseudo::isLogicImmOpRedundant(unsigned Op,
+ unsigned ImmVal) const {
// ANDI Rd, 0xff is redundant.
if (Op == AVR::ANDIRdK && ImmVal == 0xff)
@@ -230,8 +231,7 @@ bool AVRExpandPseudo::
return false;
}
-bool AVRExpandPseudo::
-expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
+bool AVRExpandPseudo::expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
@@ -244,20 +244,22 @@ expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
if (!isLogicImmOpRedundant(Op, Lo8)) {
- auto MIBLO = buildMI(MBB, MBBI, Op)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(SrcIsKill))
- .addImm(Lo8);
+ auto MIBLO =
+ buildMI(MBB, MBBI, Op)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(SrcIsKill))
+ .addImm(Lo8);
// SREG is always implicitly dead
MIBLO->getOperand(3).setIsDead();
}
if (!isLogicImmOpRedundant(Op, Hi8)) {
- auto MIBHI = buildMI(MBB, MBBI, Op)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(SrcIsKill))
- .addImm(Hi8);
+ auto MIBHI =
+ buildMI(MBB, MBBI, Op)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(SrcIsKill))
+ .addImm(Hi8);
if (ImpIsDead)
MIBHI->getOperand(3).setIsDead();
@@ -292,13 +294,15 @@ bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
bool ImpIsDead = MI.getOperand(3).isDead();
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(SrcIsKill));
+ auto MIBLO =
+ buildMI(MBB, MBBI, AVR::SUBIRdK)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(SrcIsKill));
- auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(SrcIsKill));
+ auto MIBHI =
+ buildMI(MBB, MBBI, AVR::SBCIRdK)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(SrcIsKill));
switch (MI.getOperand(2).getType()) {
case MachineOperand::MO_GlobalAddress: {
@@ -349,18 +353,20 @@ bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::SBCIRdK;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(SrcIsKill))
- .addImm(Lo8);
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(SrcIsKill))
+ .addImm(Lo8);
// SREG is always implicitly killed
MIBLO->getOperand(4).setIsKill();
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(SrcIsKill))
- .addImm(Hi8);
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(SrcIsKill))
+ .addImm(Hi8);
if (ImpIsDead)
MIBHI->getOperand(3).setIsDead();
@@ -409,16 +415,18 @@ bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::COMRd;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(DstIsKill));
// SREG is always implicitly dead
MIBLO->getOperand(2).setIsDead();
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(DstIsKill));
if (ImpIsDead)
MIBHI->getOperand(2).setIsDead();
@@ -481,12 +489,12 @@ bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
// Low part
buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addReg(DstLoReg, getKillRegState(DstIsKill))
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ .addReg(DstHiReg, getKillRegState(DstIsKill))
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
if (ImpIsDead)
MIBHI->getOperand(2).setIsDead();
@@ -513,15 +521,15 @@ bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addReg(DstLoReg, getKillRegState(DstIsKill))
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
// SREG is always implicitly killed
MIBLO->getOperand(3).setIsKill();
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ .addReg(DstHiReg, getKillRegState(DstIsKill))
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
if (ImpIsDead)
MIBHI->getOperand(2).setIsDead();
@@ -543,11 +551,13 @@ bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::LDIRdK;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
switch (MI.getOperand(1).getType()) {
case MachineOperand::MO_GlobalAddress: {
@@ -592,11 +602,13 @@ bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::LDSRdK;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
switch (MI.getOperand(1).getType()) {
case MachineOperand::MO_GlobalAddress: {
@@ -656,9 +668,9 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
// Load high byte.
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addImm(1);
+ .addReg(CurDstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill))
+ .addImm(1);
if (TmpReg) {
// Move the high byte into the final destination.
@@ -689,15 +701,17 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg, RegState::Define)
- .addReg(SrcReg, RegState::Kill);
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg, RegState::Define)
+ .addReg(SrcReg, RegState::Kill);
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
- .addReg(SrcReg, RegState::Kill);
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
+ .addReg(SrcReg, RegState::Kill);
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -720,15 +734,17 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg, RegState::Define)
- .addReg(SrcReg, RegState::Kill);
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg, RegState::Define)
+ .addReg(SrcReg, RegState::Kill);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
- .addReg(SrcReg, RegState::Kill);
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
+ .addReg(SrcReg, RegState::Kill);
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -750,8 +766,8 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::LDDRdPtrQ;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
- // allowed for the instruction, 62 is the limit here.
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
+ // highest Imm value allowed for the instruction, 62 is the limit here.
assert(Imm <= 62 && "Offset is out of range");
// Use a temporary register if src and dst registers are the same.
@@ -763,9 +779,9 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
// Load low byte.
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(CurDstLoReg, RegState::Define)
- .addReg(SrcReg)
- .addImm(Imm);
+ .addReg(CurDstLoReg, RegState::Define)
+ .addReg(SrcReg)
+ .addImm(Imm);
// Push low byte onto stack if necessary.
if (TmpReg)
@@ -773,9 +789,9 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
// Load high byte.
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addImm(Imm + 1);
+ .addReg(CurDstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill))
+ .addImm(Imm + 1);
if (TmpReg) {
// Move the high byte into the final destination.
@@ -813,8 +829,8 @@ bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
// Load low byte.
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(CurDstLoReg, RegState::Define)
- .addReg(SrcReg);
+ .addReg(CurDstLoReg, RegState::Define)
+ .addReg(SrcReg);
// Push low byte onto stack if necessary.
if (TmpReg)
@@ -822,8 +838,8 @@ bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
// Load high byte.
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill));
+ .addReg(CurDstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
if (TmpReg) {
// Move the high byte into the final destination.
@@ -845,15 +861,15 @@ bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
llvm_unreachable("wide LPMPi is unimplemented");
}
-template<typename Func>
+template <typename Func>
bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
// Remove the pseudo instruction.
MachineInstr &MI = *MBBI;
// Store the SREG.
buildMI(MBB, MBBI, AVR::INRdA)
- .addReg(SCRATCH_REGISTER, RegState::Define)
- .addImm(SREG_ADDR);
+ .addReg(SCRATCH_REGISTER, RegState::Define)
+ .addImm(SREG_ADDR);
// Disable exceptions.
buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
@@ -861,58 +877,52 @@ bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
f(MI);
// Restore the status reg.
- buildMI(MBB, MBBI, AVR::OUTARr)
- .addImm(SREG_ADDR)
- .addReg(SCRATCH_REGISTER);
+ buildMI(MBB, MBBI, AVR::OUTARr).addImm(SREG_ADDR).addReg(SCRATCH_REGISTER);
MI.eraseFromParent();
return true;
}
-template<typename Func>
-bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
- Block &MBB,
- BlockIt MBBI,
- Func f) {
+template <typename Func>
+bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
+ BlockIt MBBI, Func f) {
return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
- auto Op1 = MI.getOperand(0);
- auto Op2 = MI.getOperand(1);
+ auto Op1 = MI.getOperand(0);
+ auto Op2 = MI.getOperand(1);
- MachineInstr &NewInst =
- *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
- f(NewInst);
+ MachineInstr &NewInst =
+ *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
+ f(NewInst);
});
}
-bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
- Block &MBB,
+bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
BlockIt MBBI) {
return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
}
bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width,
- unsigned ArithOpcode,
- Block &MBB,
+ unsigned ArithOpcode, Block &MBB,
BlockIt MBBI) {
return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
- auto DstReg = MI.getOperand(0).getReg();
- auto PtrOp = MI.getOperand(1);
- auto SrcReg = MI.getOperand(2).getReg();
+ auto DstReg = MI.getOperand(0).getReg();
+ auto PtrOp = MI.getOperand(1);
+ auto SrcReg = MI.getOperand(2).getReg();
- unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
- unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
+ unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
+ unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
- // FIXME: this returns the new value (after the operation), not the old
- // value as the atomicrmw instruction is supposed to do!
+ // FIXME: this returns the new value (after the operation), not the old
+ // value as the atomicrmw instruction is supposed to do!
- // Create the load
- buildMI(MBB, MBBI, LoadOpcode, DstReg).addReg(PtrOp.getReg());
+ // Create the load
+ buildMI(MBB, MBBI, LoadOpcode, DstReg).addReg(PtrOp.getReg());
- // Create the arithmetic op
- buildMI(MBB, MBBI, ArithOpcode, DstReg).addReg(DstReg).addReg(SrcReg);
+ // Create the arithmetic op
+ buildMI(MBB, MBBI, ArithOpcode, DstReg).addReg(DstReg).addReg(SrcReg);
- // Create the store
- buildMI(MBB, MBBI, StoreOpcode).add(PtrOp).addReg(DstReg);
+ // Create the store
+ buildMI(MBB, MBBI, StoreOpcode).add(PtrOp).addReg(DstReg);
});
}
@@ -924,8 +934,7 @@ Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
RS.forward(MI);
BitVector Candidates =
- TRI->getAllocatableSet
- (*MBB.getParent(), &AVR::GPR8RegClass);
+ TRI->getAllocatableSet(*MBB.getParent(), &AVR::GPR8RegClass);
// Exclude all the registers being used by the instruction.
for (MachineOperand &MO : MI.operands()) {
@@ -942,77 +951,77 @@ Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
return Reg;
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd8>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(8, AVR::ADDRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd16>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(16, AVR::ADDWRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadSub8>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(8, AVR::SUBRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadSub16>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(16, AVR::SUBWRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd8>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(8, AVR::ANDRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd16>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(16, AVR::ANDWRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadOr8>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(8, AVR::ORRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadOr16>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(16, AVR::ORWRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadXor8>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(8, AVR::EORRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicLoadXor16>(Block &MBB, BlockIt MBBI) {
return expandAtomicArithmeticOp(16, AVR::EORWRdRr, MBB, MBBI);
}
-template<>
+template <>
bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
// On AVR, there is only one core and so atomic fences do nothing.
MBBI->eraseFromParent();
@@ -1077,15 +1086,15 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::STDPtrQRr;
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
- //:TODO: need to reverse this order like inw and stsw?
+ //: TODO: need to reverse this order like inw and stsw?
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstReg, getUndefRegState(DstIsUndef))
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addReg(DstReg, getUndefRegState(DstIsUndef))
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstReg, getUndefRegState(DstIsUndef))
- .addImm(1)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ .addReg(DstReg, getUndefRegState(DstIsUndef))
+ .addImm(1)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1110,16 +1119,17 @@ bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstReg, RegState::Define)
- .addReg(DstReg, RegState::Kill)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill))
- .addImm(Imm);
+ .addReg(DstReg, RegState::Define)
+ .addReg(DstReg, RegState::Kill)
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+ .addImm(Imm);
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg, RegState::Kill)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill))
- .addImm(Imm);
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, RegState::Kill)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+ .addImm(Imm);
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1144,16 +1154,17 @@ bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstReg, RegState::Define)
- .addReg(DstReg, RegState::Kill)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill))
- .addImm(Imm);
+ .addReg(DstReg, RegState::Define)
+ .addReg(DstReg, RegState::Kill)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+ .addImm(Imm);
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg, RegState::Kill)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill))
- .addImm(Imm);
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, RegState::Kill)
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+ .addImm(Imm);
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1175,19 +1186,19 @@ bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::STDPtrQRr;
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
- // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
- // allowed for the instruction, 62 is the limit here.
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
+ // highest Imm value allowed for the instruction, 62 is the limit here.
assert(Imm <= 62 && "Offset is out of range");
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstReg)
- .addImm(Imm)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addReg(DstReg)
+ .addImm(Imm)
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstReg, getKillRegState(DstIsKill))
- .addImm(Imm + 1)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addImm(Imm + 1)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1207,17 +1218,19 @@ bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::INRdA;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
- // allowed for the instruction, 62 is the limit here.
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
+ // highest Imm value allowed for the instruction, 62 is the limit here.
assert(Imm <= 62 && "Address is out of range");
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addImm(Imm);
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addImm(Imm);
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addImm(Imm + 1);
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addImm(Imm + 1);
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1237,18 +1250,18 @@ bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
unsigned OpHi = AVR::OUTARr;
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
- // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
- // allowed for the instruction, 62 is the limit here.
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
+ // highest Imm value allowed for the instruction, 62 is the limit here.
assert(Imm <= 62 && "Address is out of range");
// 16 bit I/O writes need the high byte first
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addImm(Imm + 1)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill));
+ .addImm(Imm + 1)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill));
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addImm(Imm)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+ .addImm(Imm)
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill));
MIBLO.setMemRefs(MI.memoperands());
MIBHI.setMemRefs(MI.memoperands());
@@ -1270,13 +1283,13 @@ bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
// Low part
buildMI(MBB, MBBI, OpLo)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill))
- .setMIFlags(Flags);
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+ .setMIFlags(Flags);
// High part
buildMI(MBB, MBBI, OpHi)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill))
- .setMIFlags(Flags);
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+ .setMIFlags(Flags);
MI.eraseFromParent();
return true;
@@ -1319,15 +1332,15 @@ bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
// Shift part
buildMI(MBB, MBBI, OpShift)
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg)
- .addReg(DstReg);
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg)
+ .addReg(DstReg);
// Add the carry bit
auto MIB = buildMI(MBB, MBBI, OpCarry)
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg)
- .addReg(ZERO_REGISTER);
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg)
+ .addReg(ZERO_REGISTER);
// SREG is always implicitly killed
MIB->getOperand(2).setIsKill();
@@ -1378,14 +1391,15 @@ bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
// Low part
buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg)
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg)
+ .addReg(DstLoReg, getKillRegState(DstIsKill));
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg)
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ auto MIBHI =
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg)
+ .addReg(DstHiReg, getKillRegState(DstIsKill));
if (ImpIsDead)
MIBHI->getOperand(3).setIsDead();
@@ -1554,12 +1568,13 @@ bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
// High part
buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(DstIsKill));
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(DstIsKill));
if (ImpIsDead)
MIBLO->getOperand(2).setIsDead();
@@ -1740,12 +1755,13 @@ bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
// High part
buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, getKillRegState(DstIsKill));
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ auto MIBLO =
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg, getKillRegState(DstIsKill));
if (ImpIsDead)
MIBLO->getOperand(2).setIsDead();
@@ -1817,7 +1833,8 @@ bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::RORRd)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstReg, getKillRegState(DstIsKill))
- ->getOperand(3).setIsUndef(true);
+ ->getOperand(3)
+ .setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1867,7 +1884,8 @@ bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstReg, getKillRegState(DstIsKill))
.addReg(DstReg, getKillRegState(DstIsKill))
- ->getOperand(4).setIsUndef(true);
+ ->getOperand(4)
+ .setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1918,10 +1936,11 @@ bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
.addReg(DstReg, getKillRegState(DstIsKill))
.addReg(DstReg, getKillRegState(DstIsKill));
- auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg, getKillRegState(DstIsKill))
- .addReg(DstReg, getKillRegState(DstIsKill));
+ auto MIRRC =
+ buildMI(MBB, MBBI, AVR::SBCRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
if (ImpIsDead)
MIRRC->getOperand(3).setIsDead();
@@ -1970,9 +1989,10 @@ template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
if (SrcReg != DstLoReg) {
- auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg);
+ auto MOV =
+ buildMI(MBB, MBBI, AVR::MOVRdRr)
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg);
if (SrcReg == DstHiReg) {
MOV->getOperand(1).setIsKill();
@@ -1981,19 +2001,20 @@ template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
if (SrcReg != DstHiReg) {
buildMI(MBB, MBBI, AVR::MOVRdRr)
- .addReg(DstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill));
+ .addReg(DstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
}
buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
- .addReg(DstHiReg, RegState::Define)
- .addReg(DstHiReg)
- .addReg(DstHiReg, RegState::Kill);
+ .addReg(DstHiReg, RegState::Define)
+ .addReg(DstHiReg)
+ .addReg(DstHiReg, RegState::Kill);
- auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, RegState::Kill)
- .addReg(DstHiReg, RegState::Kill);
+ auto SBC =
+ buildMI(MBB, MBBI, AVR::SBCRdRr)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, RegState::Kill)
+ .addReg(DstHiReg, RegState::Kill);
if (ImpIsDead)
SBC->getOperand(3).setIsDead();
@@ -2025,14 +2046,15 @@ template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
if (SrcReg != DstLoReg) {
buildMI(MBB, MBBI, AVR::MOVRdRr)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(SrcReg, getKillRegState(SrcIsKill));
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
}
- auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, RegState::Kill | RegState::Undef)
- .addReg(DstHiReg, RegState::Kill | RegState::Undef);
+ auto EOR =
+ buildMI(MBB, MBBI, AVR::EORRdRr)
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstHiReg, RegState::Kill | RegState::Undef)
+ .addReg(DstHiReg, RegState::Kill | RegState::Undef);
if (ImpIsDead)
EOR->getOperand(3).setIsDead();
@@ -2054,15 +2076,15 @@ bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
// Low part
buildMI(MBB, MBBI, OpLo)
- .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addImm(0x3d)
- .setMIFlags(Flags);
+ .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addImm(0x3d)
+ .setMIFlags(Flags);
// High part
buildMI(MBB, MBBI, OpHi)
- .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addImm(0x3e)
- .setMIFlags(Flags);
+ .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addImm(0x3e)
+ .setMIFlags(Flags);
MI.eraseFromParent();
return true;
@@ -2078,26 +2100,26 @@ bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
buildMI(MBB, MBBI, AVR::INRdA)
- .addReg(AVR::R0, RegState::Define)
- .addImm(SREG_ADDR)
- .setMIFlags(Flags);
+ .addReg(AVR::R0, RegState::Define)
+ .addImm(SREG_ADDR)
+ .setMIFlags(Flags);
buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
buildMI(MBB, MBBI, AVR::OUTARr)
- .addImm(0x3e)
- .addReg(SrcHiReg, getKillRegState(SrcIsKill))
- .setMIFlags(Flags);
+ .addImm(0x3e)
+ .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+ .setMIFlags(Flags);
buildMI(MBB, MBBI, AVR::OUTARr)
- .addImm(SREG_ADDR)
- .addReg(AVR::R0, RegState::Kill)
- .setMIFlags(Flags);
+ .addImm(SREG_ADDR)
+ .addReg(AVR::R0, RegState::Kill)
+ .setMIFlags(Flags);
buildMI(MBB, MBBI, AVR::OUTARr)
- .addImm(0x3d)
- .addReg(SrcLoReg, getKillRegState(SrcIsKill))
- .setMIFlags(Flags);
+ .addImm(0x3d)
+ .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+ .setMIFlags(Flags);
MI.eraseFromParent();
return true;
@@ -2107,8 +2129,8 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
int Opcode = MBBI->getOpcode();
-#define EXPAND(Op) \
- case Op: \
+#define EXPAND(Op) \
+ case Op: \
return expand<Op>(MBB, MI)
switch (Opcode) {
@@ -2132,7 +2154,7 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
EXPAND(AVR::LDWRdPtr);
EXPAND(AVR::LDWRdPtrPi);
EXPAND(AVR::LDWRdPtrPd);
- case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
+ case AVR::LDDWRdYQ: //: FIXME: remove this once PR13375 gets fixed
EXPAND(AVR::LDDWRdPtrQ);
EXPAND(AVR::LPMWRdZ);
EXPAND(AVR::LPMWRdZPi);
@@ -2184,8 +2206,8 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
} // end of anonymous namespace
-INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo",
- AVR_EXPAND_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME,
+ false, false)
namespace llvm {
FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
index 89ed30e8bcdb0..9e320adfb5171 100644
--- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
@@ -361,13 +361,13 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
// values, etc) is tricky and thus left to be optimized in the future.
BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
- MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(AVR::SUBIWRdK), AVR::R31R30)
- .addReg(AVR::R31R30, RegState::Kill)
- .addImm(Amount);
+ MachineInstr *New =
+ BuildMI(MBB, MI, DL, TII.get(AVR::SUBIWRdK), AVR::R31R30)
+ .addReg(AVR::R31R30, RegState::Kill)
+ .addImm(Amount);
New->getOperand(3).setIsDead();
- BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
- .addReg(AVR::R31R30);
+ BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP).addReg(AVR::R31R30);
// Make sure the remaining stack stores are converted to real store
// instructions.
@@ -536,4 +536,3 @@ char AVRDynAllocaSR::ID = 0;
FunctionPass *createAVRDynAllocaSRPass() { return new AVRDynAllocaSR(); }
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index df382d5537534..7ec2629ab45d8 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -156,9 +156,9 @@ bool AVRDAGToDAGISel::selectIndexedLoad(SDNode *N) {
return false;
}
- SDNode *ResNode = CurDAG->getMachineNode(Opcode, SDLoc(N), VT,
- PtrVT, MVT::Other,
- LD->getBasePtr(), LD->getChain());
+ SDNode *ResNode =
+ CurDAG->getMachineNode(Opcode, SDLoc(N), VT, PtrVT, MVT::Other,
+ LD->getBasePtr(), LD->getChain());
ReplaceUses(N, ResNode);
CurDAG->RemoveDeadNode(N);
@@ -199,12 +199,11 @@ unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD,
return Opcode;
}
-bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintCode,
- std::vector<SDValue> &OutOps) {
+bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
assert((ConstraintCode == InlineAsm::Constraint_m ||
- ConstraintCode == InlineAsm::Constraint_Q) &&
- "Unexpected asm memory constraint");
+ ConstraintCode == InlineAsm::Constraint_Q) &&
+ "Unexpected asm memory constraint");
MachineRegisterInfo &RI = MF->getRegInfo();
const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
@@ -276,7 +275,8 @@ bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
}
if (ImmNode->getValueType(0) != MVT::i8) {
- Disp = CurDAG->getTargetConstant(ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8);
+ Disp = CurDAG->getTargetConstant(
+ ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8);
} else {
Disp = ImmOp;
}
@@ -309,11 +309,10 @@ template <> bool AVRDAGToDAGISel::select<ISD::FrameIndex>(SDNode *N) {
// effective address of the final stack slot.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI =
- CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy(DL));
+ CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy(DL));
- CurDAG->SelectNodeTo(N, AVR::FRMIDX,
- getTargetLowering()->getPointerTy(DL), TFI,
- CurDAG->getTargetConstant(0, SDLoc(N), MVT::i16));
+ CurDAG->SelectNodeTo(N, AVR::FRMIDX, getTargetLowering()->getPointerTy(DL),
+ TFI, CurDAG->getTargetConstant(0, SDLoc(N), MVT::i16));
return true;
}
@@ -380,8 +379,8 @@ template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) {
// Check if the opcode can be converted into an indexed load.
if (unsigned LPMOpc = selectIndexedProgMemLoad(LD, VT)) {
// It is legal to fold the load into an indexed load.
- ResNode = CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, Ptr,
- RegZ);
+ ResNode =
+ CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, Ptr, RegZ);
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
} else {
// Selecting an indexed load is not legal, fallback to a normal load.
@@ -391,8 +390,8 @@ template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) {
Ptr, RegZ);
break;
case MVT::i16:
- ResNode = CurDAG->getMachineNode(AVR::LPMWRdZ, DL, MVT::i16,
- MVT::Other, Ptr, RegZ);
+ ResNode = CurDAG->getMachineNode(AVR::LPMWRdZ, DL, MVT::i16, MVT::Other,
+ Ptr, RegZ);
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
break;
default:
@@ -441,7 +440,7 @@ template <> bool AVRDAGToDAGISel::select<AVRISD::CALL>(SDNode *N) {
Ops.push_back(Chain.getValue(1));
SDNode *ResNode =
- CurDAG->getMachineNode(AVR::ICALL, DL, MVT::Other, MVT::Glue, Ops);
+ CurDAG->getMachineNode(AVR::ICALL, DL, MVT::Other, MVT::Glue, Ops);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
@@ -532,16 +531,23 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) {
switch (Opcode) {
// Nodes we fully handle.
- case ISD::FrameIndex: return select<ISD::FrameIndex>(N);
- case ISD::BRIND: return select<ISD::BRIND>(N);
+ case ISD::FrameIndex:
+ return select<ISD::FrameIndex>(N);
+ case ISD::BRIND:
+ return select<ISD::BRIND>(N);
case ISD::UMUL_LOHI:
- case ISD::SMUL_LOHI: return selectMultiplication(N);
+ case ISD::SMUL_LOHI:
+ return selectMultiplication(N);
// Nodes we handle partially. Other cases are autogenerated
- case ISD::STORE: return select<ISD::STORE>(N);
- case ISD::LOAD: return select<ISD::LOAD>(N);
- case AVRISD::CALL: return select<AVRISD::CALL>(N);
- default: return false;
+ case ISD::STORE:
+ return select<ISD::STORE>(N);
+ case ISD::LOAD:
+ return select<ISD::LOAD>(N);
+ case AVRISD::CALL:
+ return select<AVRISD::CALL>(N);
+ default:
+ return false;
}
}
@@ -551,4 +557,3 @@ FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index ce50ed0bcfd74..cc328cdacbf67 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -13,8 +13,8 @@
#include "AVRISelLowering.h"
-#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -232,8 +232,8 @@ AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
}
const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
-#define NODE(name) \
- case AVRISD::name: \
+#define NODE(name) \
+ case AVRISD::name: \
return #name
switch (Opcode) {
@@ -269,7 +269,7 @@ EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
}
SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
- //:TODO: this function has to be completely rewritten to produce optimal
+ //: TODO: this function has to be completely rewritten to produce optimal
// code, for now it's producing very long but correct code.
unsigned Opc8;
const SDNode *N = Op.getNode();
@@ -527,7 +527,8 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
"LHS and RHS have
diff erent types");
assert(((LHS.getSimpleValueType() == MVT::i16) ||
- (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type");
+ (LHS.getSimpleValueType() == MVT::i8)) &&
+ "invalid comparison type");
SDValue Cmp;
@@ -856,7 +857,8 @@ void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
/// by AM is legal for this target, for a load/store of the specified type.
bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
- unsigned AS, Instruction *I) const {
+ unsigned AS,
+ Instruction *I) const {
int64_t Offs = AM.BaseOffs;
// Allow absolute addresses.
@@ -1003,14 +1005,13 @@ static const MCPhysReg RegList8[] = {
AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
static const MCPhysReg RegList16[] = {
- AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
- AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
- AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
- AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
- AVR::R10R9, AVR::R9R8};
+ AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
+ AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
+ AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
+ AVR::R11R10, AVR::R10R9, AVR::R9R8};
static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
- "8-bit and 16-bit register arrays must be of equal length");
+ "8-bit and 16-bit register arrays must be of equal length");
/// Analyze incoming and outgoing function arguments. We need custom C++ code
/// to handle special constraints in the ABI.
@@ -1084,10 +1085,11 @@ analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
/// Count the total number of bytes needed to pass or return these arguments.
template <typename ArgT>
-static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
+static unsigned
+getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
unsigned TotalBytes = 0;
- for (const ArgT& Arg : Args) {
+ for (const ArgT &Arg : Args) {
TotalBytes += Arg.VT.getStoreSize();
}
return TotalBytes;
@@ -1102,7 +1104,8 @@ static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
unsigned NumArgs = Args.size();
unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
// CanLowerReturn() guarantees this assertion.
- assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered");
+ assert(TotalBytes <= 8 &&
+ "return values greater than 8 bytes cannot be lowered");
// GCC-ABI says that the size is rounded up to the next even number,
// but actually once it is more than 4 it will always round up to 8.
@@ -1406,8 +1409,8 @@ SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
///
SDValue AVRTargetLowering::LowerCallResult(
SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const {
+ const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
+ SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
@@ -1495,9 +1498,7 @@ AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
unsigned RetOpc =
- AFI->isInterruptOrSignalHandler()
- ? AVRISD::RETI_FLAG
- : AVRISD::RET_FLAG;
+ AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
RetOps[0] = Chain; // Update chain.
@@ -1571,8 +1572,10 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineFunction::iterator I;
- for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
- if (I != F->end()) ++I;
+ for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
+ ;
+ if (I != F->end())
+ ++I;
// Create loop block.
MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -1635,8 +1638,7 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
.addReg(ShiftReg2)
.addMBB(LoopBB);
- BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2)
- .addReg(ShiftAmtReg);
+ BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
MI.eraseFromParent(); // The pseudo instruction is gone now.
@@ -1724,8 +1726,10 @@ AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator I;
- for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
- if (I != MF->end()) ++I;
+ for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
+ ;
+ if (I != MF->end())
+ ++I;
MF->insert(I, trueMBB);
MF->insert(I, falseMBB);
@@ -1747,11 +1751,12 @@ AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
falseMBB->addSuccessor(trueMBB);
// Set up the Phi node to determine where we came from
- BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
- .addReg(MI.getOperand(1).getReg())
- .addMBB(MBB)
- .addReg(MI.getOperand(2).getReg())
- .addMBB(falseMBB) ;
+ BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
+ MI.getOperand(0).getReg())
+ .addReg(MI.getOperand(1).getReg())
+ .addMBB(MBB)
+ .addReg(MI.getOperand(2).getReg())
+ .addMBB(falseMBB);
MI.eraseFromParent(); // The pseudo instruction is gone now.
return trueMBB;
@@ -1778,9 +1783,12 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const {
case 'w': // Special upper register pairs
return C_RegisterClass;
case 't': // Temporary register
- case 'x': case 'X': // Pointer register pair X
- case 'y': case 'Y': // Pointer register pair Y
- case 'z': case 'Z': // Pointer register pair Z
+ case 'x':
+ case 'X': // Pointer register pair X
+ case 'y':
+ case 'Y': // Pointer register pair Y
+ case 'z':
+ case 'Z': // Pointer register pair Z
return C_Register;
case 'Q': // A memory address based on Y or Z pointer with displacement.
return C_Memory;
@@ -1841,9 +1849,12 @@ AVRTargetLowering::getSingleConstraintMatchWeight(
case 'q':
case 't':
case 'w':
- case 'x': case 'X':
- case 'y': case 'Y':
- case 'z': case 'Z':
+ case 'x':
+ case 'X':
+ case 'y':
+ case 'Y':
+ case 'z':
+ case 'Z':
weight = CW_SpecificReg;
break;
case 'G':
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index 8130cf045fa83..3ae036b66bcbe 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -133,11 +133,11 @@ class AVRTargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- Register getRegisterByName(const char* RegName, LLT VT,
+ Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
- bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL)
- const override {
+ bool shouldSplitFunctionArgumentsAsLittleEndian(
+ const DataLayout &DL) const override {
return false;
}
@@ -179,7 +179,6 @@ class AVRTargetLowering : public TargetLowering {
SmallVectorImpl<SDValue> &InVals) const;
protected:
-
const AVRSubtarget &Subtarget;
private:
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
index 6eb49076efb09..2bcbcdfbf925c 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -11,8 +11,8 @@
//===----------------------------------------------------------------------===//
// A generic AVR instruction.
-class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
-{
+class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : Instruction {
let Namespace = "AVR";
dag OutOperandList = outs;
@@ -25,8 +25,7 @@ class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
/// A 16-bit AVR instruction.
class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst<outs, ins, asmstr, pattern>
-{
+ : AVRInst<outs, ins, asmstr, pattern> {
field bits<16> Inst;
let Size = 2;
@@ -34,8 +33,7 @@ class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
/// a 32-bit AVR instruction.
class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst<outs, ins, asmstr, pattern>
-{
+ : AVRInst<outs, ins, asmstr, pattern> {
field bits<32> Inst;
let Size = 4;
@@ -50,8 +48,7 @@ class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
// is defined as a pseudo instruction. In AVRExpandPseudoInsts.cpp,
// the instruction is then replaced by two add instructions - one for each byte.
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
let Pattern = pattern;
let isPseudo = 1;
@@ -67,28 +64,26 @@ class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
// (Accepts all registers)
//===----------------------------------------------------------------------===//
class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
- list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
-{
+ list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<5> rr;
- let Inst{15-12} = opcode;
- let Inst{11-10} = f;
+ let Inst{15 - 12} = opcode;
+ let Inst{11 - 10} = f;
let Inst{9} = rr{4};
- let Inst{8-4} = rd;
- let Inst{3-0} = rr{3-0};
+ let Inst{8 - 4} = rd;
+ let Inst{3 - 0} = rr{3 - 0};
}
class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
- list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
-{
+ list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> rd;
- let Inst{15-12} = opcode;
- let Inst{11-10} = f;
+ let Inst{15 - 12} = opcode;
+ let Inst{11 - 10} = f;
let Inst{9} = rd{4};
- let Inst{8-4} = rd;
- let Inst{3-0} = rd{3-0};
+ let Inst{8 - 4} = rd;
+ let Inst{3 - 0} = rd{3 - 0};
}
//===----------------------------------------------------------------------===//
@@ -96,19 +91,18 @@ class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
// <|1001|001r|rrrr|0ttt>
//===----------------------------------------------------------------------===//
class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> rd;
- let Inst{15-12} = 0b1001;
+ let Inst{15 - 12} = 0b1001;
- let Inst{11-9} = 0b001;
+ let Inst{11 - 9} = 0b001;
let Inst{8} = rd{4};
- let Inst{7-4} = rd{3-0};
+ let Inst{7 - 4} = rd{3 - 0};
let Inst{3} = 0;
- let Inst{2-0} = t;
+ let Inst{2 - 0} = t;
}
//===----------------------------------------------------------------------===//
@@ -119,15 +113,14 @@ class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Only accepts r16-r31)
//===----------------------------------------------------------------------===//
class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<4> rd;
bits<8> k;
- let Inst{15-12} = opcode;
- let Inst{11-8} = k{7-4};
- let Inst{7-4} = rd{3-0};
- let Inst{3-0} = k{3-0};
+ let Inst{15 - 12} = opcode;
+ let Inst{11 - 8} = k{7 - 4};
+ let Inst{7 - 4} = rd{3 - 0};
+ let Inst{3 - 0} = k{3 - 0};
let isAsCheapAsAMove = 1;
}
@@ -140,14 +133,13 @@ class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Accepts all registers)
//===----------------------------------------------------------------------===//
class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
- list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
-{
+ list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
- let Inst{15-12} = opcode;
- let Inst{11-9} = f{6-4};
- let Inst{8-4} = d;
- let Inst{3-0} = f{3-0};
+ let Inst{15 - 12} = opcode;
+ let Inst{11 - 9} = f{6 - 4};
+ let Inst{8 - 4} = d;
+ let Inst{3 - 0} = f{3 - 0};
let DecoderMethod = "decodeFRd";
}
@@ -160,23 +152,22 @@ class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
// p = pointer register (1 bit) [1 for Y, 0 for Z]
//===----------------------------------------------------------------------===//
class FSTDLDD<bit type, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<7> memri;
bits<5> reg; // the GP register
- let Inst{15-14} = 0b10;
+ let Inst{15 - 14} = 0b10;
let Inst{13} = memri{5};
let Inst{12} = 0;
- let Inst{11-10} = memri{4-3};
+ let Inst{11 - 10} = memri{4 - 3};
let Inst{9} = type;
let Inst{8} = reg{4};
- let Inst{7-4} = reg{3-0};
+ let Inst{7 - 4} = reg{3 - 0};
let Inst{3} = memri{6};
- let Inst{2-0} = memri{2-0};
+ let Inst{2 - 0} = memri{2 - 0};
}
//===---------------------------------------------------------------------===//
@@ -190,26 +181,24 @@ class FSTDLDD<bit type, dag outs, dag ins, string asmstr, list<dag> pattern>
// Note that the bit labelled 'i' above does not follow a simple pattern,
// so there exists a post encoder method to set it manually.
//===---------------------------------------------------------------------===//
-class FSTLD<bit type, bits<2> mode, dag outs, dag ins,
- string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+class FSTLD<bit type, bits<2> mode, dag outs, dag ins, string asmstr,
+ list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<2> ptrreg;
bits<5> reg;
- let Inst{15-13} = 0b100;
+ let Inst{15 - 13} = 0b100;
// This bit varies depending on the arguments and the mode.
// We have a post encoder method to set this bit manually.
let Inst{12} = 0;
- let Inst{11-10} = 0b00;
+ let Inst{11 - 10} = 0b00;
let Inst{9} = type;
let Inst{8} = reg{4};
- let Inst{7-4} = reg{3-0};
+ let Inst{7 - 4} = reg{3 - 0};
- let Inst{3-2} = ptrreg{1-0};
- let Inst{1-0} = mode{1-0};
+ let Inst{3 - 2} = ptrreg{1 - 0};
+ let Inst{1 - 0} = mode{1 - 0};
let PostEncoderMethod = "loadStorePostEncoder";
}
@@ -223,22 +212,21 @@ class FSTLD<bit type, bits<2> mode, dag outs, dag ins,
// p = is postincrement
//===---------------------------------------------------------------------===//
class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
- bits<5> reg;
+ : AVRInst16<outs, ins, asmstr, pattern> {
+ bits<5> reg;
- let Inst{15-12} = 0b1001;
+ let Inst{15 - 12} = 0b1001;
- let Inst{11-9} = 0b000;
- let Inst{8} = reg{4};
+ let Inst{11 - 9} = 0b000;
+ let Inst{8} = reg{4};
- let Inst{7-4} = reg{3-0};
+ let Inst{7 - 4} = reg{3 - 0};
- let Inst{3-2} = 0b01;
- let Inst{1} = e;
- let Inst{0} = p;
+ let Inst{3 - 2} = 0b01;
+ let Inst{1} = e;
+ let Inst{0} = p;
- let DecoderMethod = "decodeFLPMX";
+ let DecoderMethod = "decodeFLPMX";
}
//===----------------------------------------------------------------------===//
@@ -248,14 +236,13 @@ class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Only accepts even registers)
//===----------------------------------------------------------------------===//
class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
bits<5> r;
- let Inst{15-8} = 0b00000001;
- let Inst{7-4} = d{4-1};
- let Inst{3-0} = r{4-1};
+ let Inst{15 - 8} = 0b00000001;
+ let Inst{7 - 4} = d{4 - 1};
+ let Inst{3 - 0} = r{4 - 1};
let DecoderMethod = "decodeFMOVWRdRr";
}
@@ -267,15 +254,14 @@ class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
// (Only accepts r16-r31)
//===----------------------------------------------------------------------===//
class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
- bits<5> rd; // accept 5 bits but only encode the lower 4
- bits<5> rr; // accept 5 bits but only encode the lower 4
+ : AVRInst16<outs, ins, asmstr, pattern> {
+ bits<5> rd; // accept 5 bits but only encode the lower 4
+ bits<5> rr; // accept 5 bits but only encode the lower 4
- let Inst{15-9} = 0b0000001;
+ let Inst{15 - 9} = 0b0000001;
let Inst{8} = f;
- let Inst{7-4} = rd{3-0};
- let Inst{3-0} = rr{3-0};
+ let Inst{7 - 4} = rd{3 - 0};
+ let Inst{3 - 0} = rr{3 - 0};
let DecoderMethod = "decodeFMUL2RdRr";
}
@@ -291,21 +277,19 @@ class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
// ddd = destination register
// rrr = source register
class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<3> rd;
bits<3> rr;
- let Inst{15-8} = 0b00000011;
+ let Inst{15 - 8} = 0b00000011;
let Inst{7} = f{1};
- let Inst{6-4} = rd;
+ let Inst{6 - 4} = rd;
let Inst{3} = f{0};
- let Inst{2-0} = rr;
+ let Inst{2 - 0} = rr;
let DecoderMethod = "decodeFFMULRdRr";
}
-
//===----------------------------------------------------------------------===//
// Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
// f = secondary opcode = 1 bit
@@ -314,16 +298,15 @@ class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Only accepts r25:24 r27:26 r29:28 r31:30)
//===----------------------------------------------------------------------===//
class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
- bits<5> dst; // accept 5 bits but only encode bits 1 and 2
+ : AVRInst16<outs, ins, asmstr, pattern> {
+ bits<5> dst; // accept 5 bits but only encode bits 1 and 2
bits<6> k;
- let Inst{15-9} = 0b1001011;
+ let Inst{15 - 9} = 0b1001011;
let Inst{8} = f;
- let Inst{7-6} = k{5-4};
- let Inst{5-4} = dst{2-1};
- let Inst{3-0} = k{3-0};
+ let Inst{7 - 6} = k{5 - 4};
+ let Inst{5 - 4} = dst{2 - 1};
+ let Inst{3 - 0} = k{3 - 0};
let DecoderMethod = "decodeFWRdK";
}
@@ -335,15 +318,14 @@ class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Accepts all registers)
//===----------------------------------------------------------------------===//
class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
bits<6> A;
- let Inst{15-11} = 0b10110;
- let Inst{10-9} = A{5-4};
- let Inst{8-4} = d;
- let Inst{3-0} = A{3-0};
+ let Inst{15 - 11} = 0b10110;
+ let Inst{10 - 9} = A{5 - 4};
+ let Inst{8 - 4} = d;
+ let Inst{3 - 0} = A{3 - 0};
let DecoderMethod = "decodeFIORdA";
}
@@ -355,15 +337,14 @@ class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
// (Accepts all registers)
//===----------------------------------------------------------------------===//
class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<6> A;
bits<5> r;
- let Inst{15-11} = 0b10111;
- let Inst{10-9} = A{5-4};
- let Inst{8-4} = r;
- let Inst{3-0} = A{3-0};
+ let Inst{15 - 11} = 0b10111;
+ let Inst{10 - 9} = A{5 - 4};
+ let Inst{8 - 4} = r;
+ let Inst{3 - 0} = A{3 - 0};
let DecoderMethod = "decodeFIOARr";
}
@@ -376,20 +357,19 @@ class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
// b = bit number
//===----------------------------------------------------------------------===//
class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> A;
bits<3> b;
- let Inst{15-12} = 0b1001;
+ let Inst{15 - 12} = 0b1001;
- let Inst{11-10} = 0b10;
- let Inst{9-8} = t;
+ let Inst{11 - 10} = 0b10;
+ let Inst{9 - 8} = t;
- let Inst{7-4} = A{4-1};
+ let Inst{7 - 4} = A{4 - 1};
let Inst{3} = A{0};
- let Inst{2-0} = b{2-0};
+ let Inst{2 - 0} = b{2 - 0};
let DecoderMethod = "decodeFIOBIT";
}
@@ -402,21 +382,20 @@ class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
// b = bit
//===----------------------------------------------------------------------===//
class FRdB<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<3> b;
- let Inst{15-12} = 0b1111;
+ let Inst{15 - 12} = 0b1111;
let Inst{11} = 0b1;
- let Inst{10-9} = t;
+ let Inst{10 - 9} = t;
let Inst{8} = rd{4};
- let Inst{7-4} = rd{3-0};
+ let Inst{7 - 4} = rd{3 - 0};
let Inst{3} = 0;
- let Inst{2-0} = b;
+ let Inst{2 - 0} = b;
}
// Special encoding for the `DES K` instruction.
@@ -425,17 +404,16 @@ class FRdB<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
//
// KKKK = 4 bit immediate
class FDES<dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<4> k;
- let Inst{15-12} = 0b1001;
+ let Inst{15 - 12} = 0b1001;
- let Inst{11-8} = 0b0100;
+ let Inst{11 - 8} = 0b0100;
- let Inst{7-4} = k;
+ let Inst{7 - 4} = k;
- let Inst{3-0} = 0b1011;
+ let Inst{3 - 0} = 0b1011;
}
//===----------------------------------------------------------------------===//
@@ -444,15 +422,14 @@ class FDES<dag outs, dag ins, string asmstr, list<dag> pattern>
// k = constant address = 7 bits
// s = bit in status register = 3 bits
//===----------------------------------------------------------------------===//
-class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr,
+ list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<7> k;
- let Inst{15-11} = 0b11110;
+ let Inst{15 - 11} = 0b11110;
let Inst{10} = f;
- let Inst{9-3} = k;
- let Inst{2-0} = s;
+ let Inst{9 - 3} = k;
+ let Inst{2 - 0} = s;
}
//===----------------------------------------------------------------------===//
@@ -460,14 +437,12 @@ class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr, list<dag> patter
//===----------------------------------------------------------------------===//
class F16<bits<16> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
let Inst = opcode;
}
class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst32<outs, ins, asmstr, pattern>
-{
+ : AVRInst32<outs, ins, asmstr, pattern> {
let Inst = opcode;
}
@@ -477,13 +452,12 @@ class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
// k = constant address = 12 bits
//===----------------------------------------------------------------------===//
class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<12> k;
- let Inst{15-13} = 0b110;
+ let Inst{15 - 13} = 0b110;
let Inst{12} = f;
- let Inst{11-0} = k;
+ let Inst{11 - 0} = k;
}
//===----------------------------------------------------------------------===//
@@ -492,14 +466,13 @@ class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
// k = constant address = 22 bits
//===----------------------------------------------------------------------===//
class F32BRk<bits<3> f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst32<outs, ins, asmstr, pattern>
-{
+ : AVRInst32<outs, ins, asmstr, pattern> {
bits<22> k;
- let Inst{31-25} = 0b1001010;
- let Inst{24-20} = k{21-17};
- let Inst{19-17} = f;
- let Inst{16-0} = k{16-0};
+ let Inst{31 - 25} = 0b1001010;
+ let Inst{24 - 20} = k{21 - 17};
+ let Inst{19 - 17} = f;
+ let Inst{16 - 0} = k{16 - 0};
}
//===----------------------------------------------------------------------===//
@@ -510,38 +483,36 @@ class F32BRk<bits<3> f, dag outs, dag ins, string asmstr, list<dag> pattern>
// (Accepts all registers)
//===----------------------------------------------------------------------===//
class F32DM<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst32<outs, ins, asmstr, pattern>
-{
+ : AVRInst32<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<16> k;
- let Inst{31-28} = 0b1001;
+ let Inst{31 - 28} = 0b1001;
- let Inst{27-26} = 0b00;
+ let Inst{27 - 26} = 0b00;
let Inst{25} = f;
let Inst{24} = rd{4};
- let Inst{23-20} = rd{3-0};
+ let Inst{23 - 20} = rd{3 - 0};
- let Inst{19-16} = 0b0000;
+ let Inst{19 - 16} = 0b0000;
- let Inst{15-0} = k;
+ let Inst{15 - 0} = k;
}
// <|1001|0100|bfff|1000>
class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<3> s;
- let Inst{15-12} = 0b1001;
+ let Inst{15 - 12} = 0b1001;
- let Inst{11-8} = 0b0100;
+ let Inst{11 - 8} = 0b0100;
let Inst{7} = b;
- let Inst{6-4} = s;
+ let Inst{6 - 4} = s;
- let Inst{3-0} = 0b1000;
+ let Inst{3 - 0} = 0b1000;
}
// Set/clr bit in status flag instructions/
@@ -549,48 +520,42 @@ class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern>
// ---------------------
// <|1111|0fkk|kkkk|ksss>
class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
- : AVRInst16<outs, ins, asmstr, pattern>
-{
+ : AVRInst16<outs, ins, asmstr, pattern> {
bits<7> k;
bits<3> s;
- let Inst{15-12} = 0b1111;
+ let Inst{15 - 12} = 0b1111;
let Inst{11} = 0;
let Inst{10} = f;
- let Inst{9-8} = k{6-5};
+ let Inst{9 - 8} = k{6 - 5};
- let Inst{7-4} = k{4-1};
+ let Inst{7 - 4} = k{4 - 1};
let Inst{3} = k{0};
- let Inst{2-0} = s;
+ let Inst{2 - 0} = s;
}
class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : Pseudo<outs, ins, asmstr, pattern>
-{
+ : Pseudo<outs, ins, asmstr, pattern> {
let Defs = [SREG];
}
class StorePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : Pseudo<outs, ins, asmstr, pattern>
-{
+ : Pseudo<outs, ins, asmstr, pattern> {
let Defs = [SP];
}
class SelectPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : Pseudo<outs, ins, asmstr, pattern>
-{
+ : Pseudo<outs, ins, asmstr, pattern> {
let usesCustomInserter = 1;
let Uses = [SREG];
}
class ShiftPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : Pseudo<outs, ins, asmstr, pattern>
-{
+ : Pseudo<outs, ins, asmstr, pattern> {
let usesCustomInserter = 1;
let Defs = [SREG];
}
-
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index 06f07696bde3e..8af350b7a2397 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -55,13 +55,13 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Register DestLo, DestHi, SrcLo, SrcHi;
TRI.splitReg(DestReg, DestLo, DestHi);
- TRI.splitReg(SrcReg, SrcLo, SrcHi);
+ TRI.splitReg(SrcReg, SrcLo, SrcHi);
// Copy each individual register with the `MOV` instruction.
BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
- .addReg(SrcLo, getKillRegState(KillSrc));
+ .addReg(SrcLo, getKillRegState(KillSrc));
BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
- .addReg(SrcHi, getKillRegState(KillSrc));
+ .addReg(SrcHi, getKillRegState(KillSrc));
}
} else {
if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
@@ -83,7 +83,7 @@ unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
case AVR::LDDRdPtrQ:
- case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
+ case AVR::LDDWRdYQ: { //: FIXME: remove this once PR13375 gets fixed
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
@@ -179,7 +179,7 @@ void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opcode = AVR::LDDRdPtrQ;
} else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
// Opcode = AVR::LDDWRdPtrQ;
- //:FIXME: remove this once PR13375 gets fixed
+ //: FIXME: remove this once PR13375 gets fixed
Opcode = AVR::LDDWRdYQ;
} else {
llvm_unreachable("Cannot load this register from a stack slot!");
@@ -289,7 +289,7 @@ bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
}
// Handle unconditional branches.
- //:TODO: add here jmp
+ //: TODO: add here jmp
if (I->getOpcode() == AVR::RJMPk) {
UnCondBrIter = I;
@@ -399,9 +399,9 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
- if (BytesAdded) *BytesAdded = 0;
+ const DebugLoc &DL, int *BytesAdded) const {
+ if (BytesAdded)
+ *BytesAdded = 0;
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
@@ -421,13 +421,15 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
- if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI);
+ if (BytesAdded)
+ *BytesAdded += getInstSizeInBytes(CondMI);
++Count;
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
- if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI);
+ if (BytesAdded)
+ *BytesAdded += getInstSizeInBytes(MI);
++Count;
}
@@ -436,7 +438,8 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
- if (BytesRemoved) *BytesRemoved = 0;
+ if (BytesRemoved)
+ *BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
@@ -446,7 +449,7 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
if (I->isDebugInstr()) {
continue;
}
- //:TODO: add here the missing jmp instructions once they are implemented
+ //: TODO: add here the missing jmp instructions once they are implemented
// like jmp, {e}ijmp, and other cond branches, ...
if (I->getOpcode() != AVR::RJMPk &&
getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
@@ -454,7 +457,8 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
}
// Remove the branch.
- if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I);
+ if (BytesRemoved)
+ *BytesRemoved += getInstSizeInBytes(*I);
I->eraseFromParent();
I = MBB.end();
++Count;
@@ -490,7 +494,8 @@ unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
case TargetOpcode::INLINEASM:
case TargetOpcode::INLINEASM_BR: {
const MachineFunction &MF = *MI.getParent()->getParent();
- const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
+ const AVRTargetMachine &TM =
+ static_cast<const AVRTargetMachine &>(MF.getTarget());
const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
const TargetInstrInfo &TII = *STI.getInstrInfo();
@@ -560,15 +565,14 @@ unsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
const DebugLoc &DL,
int64_t BrOffset,
RegScavenger *RS) const {
- // This method inserts a *direct* branch (JMP), despite its name.
- // LLVM calls this method to fixup unconditional branches; it never calls
- // insertBranch or some hypothetical "insertDirectBranch".
- // See lib/CodeGen/RegisterRelaxation.cpp for details.
- // We end up here when a jump is too long for a RJMP instruction.
- auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
-
- return getInstSizeInBytes(MI);
+ // This method inserts a *direct* branch (JMP), despite its name.
+ // LLVM calls this method to fixup unconditional branches; it never calls
+ // insertBranch or some hypothetical "insertDirectBranch".
+ // See lib/CodeGen/RegisterRelaxation.cpp for details.
+ // We end up here when a jump is too long for a RJMP instruction.
+ auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
+
+ return getInstSizeInBytes(MI);
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 11f45865de541..628c21b858f2a 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -109,9 +109,9 @@ class AVRInstrInfo : public AVRGenInstrInfo {
unsigned insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
- const DebugLoc &DL,
- int64_t BrOffset,
+ const DebugLoc &DL, int64_t BrOffset,
RegScavenger *RS) const override;
+
private:
const AVRRegisterInfo RI;
};
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index c7c9656d3bfb0..c7f423292da05 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -20,12 +20,13 @@ def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
-def SDT_AVRBrcond : SDTypeProfile<0, 2,
- [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
+def SDT_AVRBrcond
+ : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
-def SDT_AVRSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
- SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
+def SDT_AVRSelectCC
+ : SDTypeProfile<1, 3,
+ [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
//===----------------------------------------------------------------------===//
// AVR Specific Node Definitions
@@ -46,12 +47,12 @@ def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
-def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond,
- [SDNPHasChain, SDNPInGlue]>;
+def AVRbrcond
+ : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;
def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
-def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
+def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
// Shift nodes.
def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
@@ -80,29 +81,31 @@ def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;
// AVR Operands, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
-def imm8_neg_XFORM : SDNodeXForm<imm,
-[{
- return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
-}]>;
+def imm8_neg_XFORM : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(
+ -N->getAPIntValue(), SDLoc(N), MVT::i8);
+ }]>;
-def imm16_neg_XFORM : SDNodeXForm<imm,
-[{
- return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
-}]>;
+def imm16_neg_XFORM
+ : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(-N->getAPIntValue(),
+ SDLoc(N), MVT::i16);
+ }]>;
-def imm0_63_neg : PatLeaf<(imm),
-[{
- int64_t val = -N->getSExtValue();
- return val >= 0 && val < 64;
-}], imm16_neg_XFORM>;
+def imm0_63_neg : PatLeaf<(imm), [{
+ int64_t val = -N->getSExtValue();
+ return val >= 0 && val < 64;
+ }],
+ imm16_neg_XFORM>;
def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
// imm_com8_XFORM - Return the complement of a imm_com8 value
-def imm_com8_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint8_t)N->getZExtValue()), SDLoc(N),
- MVT::i8);
-}]>;
+def imm_com8_XFORM
+ : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(
+ ~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8);
+ }]>;
// imm_com8 - Match an immediate that is a complement
// of a 8-bit immediate.
@@ -110,59 +113,55 @@ def imm_com8_XFORM : SDNodeXForm<imm, [{
// only used on aliases (Pat<> and InstAlias<>). The actual encoding
// is handled by the destination instructions, which use imm_com8.
def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; }
-def imm_com8 : Operand<i8> {
- let ParserMatchClass = imm_com8_asmoperand;
-}
-
-def ioaddr_XFORM : SDNodeXForm<imm,
-[{
- uint8_t offset = Subtarget->getIORegisterOffset();
- return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - offset,
- SDLoc(N), MVT::i8);
-}]>;
-
-def iobitpos8_XFORM : SDNodeXForm<imm,
-[{
- return CurDAG->getTargetConstant(Log2_32(uint8_t(N->getZExtValue())),
- SDLoc(N), MVT::i8);
-}]>;
-
-def iobitposn8_XFORM : SDNodeXForm<imm,
-[{
- return CurDAG->getTargetConstant(Log2_32(uint8_t(~N->getZExtValue())),
- SDLoc(N), MVT::i8);
-}]>;
-
-def ioaddr8 : PatLeaf<(imm),
-[{
- uint8_t offset = Subtarget->getIORegisterOffset();
- uint64_t val = N->getZExtValue() - offset;
- return val < 0x40;
-}], ioaddr_XFORM>;
-
-def lowioaddr8 : PatLeaf<(imm),
-[{
- uint8_t offset = Subtarget->getIORegisterOffset();
- uint64_t val = N->getZExtValue() - offset;
- return val < 0x20;
-}], ioaddr_XFORM>;
-
-def ioaddr16 : PatLeaf<(imm),
-[{
- uint8_t offset = Subtarget->getIORegisterOffset();
- uint64_t val = N->getZExtValue() - offset;
- return val < 0x3f;
-}], ioaddr_XFORM>;
-
-def iobitpos8 : PatLeaf<(imm),
-[{
- return isPowerOf2_32(uint8_t(N->getZExtValue()));
-}], iobitpos8_XFORM>;
-
-def iobitposn8 : PatLeaf<(imm),
-[{
- return isPowerOf2_32(uint8_t(~N->getZExtValue()));
-}], iobitposn8_XFORM>;
+def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; }
+
+def ioaddr_XFORM
+ : SDNodeXForm<imm, [{
+ uint8_t offset = Subtarget->getIORegisterOffset();
+ return CurDAG->getTargetConstant(
+ uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8);
+ }]>;
+
+def iobitpos8_XFORM
+ : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(
+ Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8);
+ }]>;
+
+def iobitposn8_XFORM : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(
+ Log2_32(uint8_t(~N->getZExtValue())),
+ SDLoc(N), MVT::i8);
+ }]>;
+
+def ioaddr8 : PatLeaf<(imm), [{
+ uint8_t offset = Subtarget->getIORegisterOffset();
+ uint64_t val = N->getZExtValue() - offset;
+ return val < 0x40;
+ }],
+ ioaddr_XFORM>;
+
+def lowioaddr8 : PatLeaf<(imm), [{
+ uint8_t offset = Subtarget->getIORegisterOffset();
+ uint64_t val = N->getZExtValue() - offset;
+ return val < 0x20;
+ }],
+ ioaddr_XFORM>;
+
+def ioaddr16 : PatLeaf<(imm), [{
+ uint8_t offset = Subtarget->getIORegisterOffset();
+ uint64_t val = N->getZExtValue() - offset;
+ return val < 0x3f;
+ }],
+ ioaddr_XFORM>;
+
+def iobitpos8
+ : PatLeaf<(imm), [{ return isPowerOf2_32(uint8_t(N->getZExtValue())); }],
+ iobitpos8_XFORM>;
+
+def iobitposn8
+ : PatLeaf<(imm), [{ return isPowerOf2_32(uint8_t(~N->getZExtValue())); }],
+ iobitposn8_XFORM>;
def MemriAsmOperand : AsmOperandClass {
let Name = "Memri";
@@ -170,8 +169,7 @@ def MemriAsmOperand : AsmOperandClass {
}
/// Address operand for `reg+imm` used by STD and LDD.
-def memri : Operand<iPTR>
-{
+def memri : Operand<iPTR> {
let MIOperandInfo = (ops PTRDISPREGS, i16imm);
let PrintMethod = "printMemri";
@@ -181,60 +179,47 @@ def memri : Operand<iPTR>
}
// Address operand for `SP+imm` used by STD{W}SPQRr
-def memspi : Operand<iPTR>
-{
- let MIOperandInfo = (ops GPRSP, i16imm);
-}
+def memspi : Operand<iPTR> { let MIOperandInfo = (ops GPRSP, i16imm); }
-def relbrtarget_7 : Operand<OtherVT>
-{
- let PrintMethod = "printPCRelImm";
- let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
+def relbrtarget_7 : Operand<OtherVT> {
+ let PrintMethod = "printPCRelImm";
+ let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
}
-def brtarget_13 : Operand<OtherVT>
-{
- let PrintMethod = "printPCRelImm";
- let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
+def brtarget_13 : Operand<OtherVT> {
+ let PrintMethod = "printPCRelImm";
+ let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
}
// The target of a 22 or 16-bit call/jmp instruction.
-def call_target : Operand<iPTR>
-{
- let EncoderMethod = "encodeCallTarget";
- let DecoderMethod = "decodeCallTarget";
+def call_target : Operand<iPTR> {
+ let EncoderMethod = "encodeCallTarget";
+ let DecoderMethod = "decodeCallTarget";
}
// A 16-bit address (which can lead to an R_AVR_16 relocation).
-def imm16 : Operand<i16>
-{
- let EncoderMethod = "encodeImm<AVR::fixup_16, 2>";
-}
+def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }
/// A 6-bit immediate used in the ADIW/SBIW instructions.
-def imm_arith6 : Operand<i16>
-{
- let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
+def imm_arith6 : Operand<i16> {
+ let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
}
/// An 8-bit immediate inside an instruction with the same format
/// as the `LDI` instruction (the `FRdK` format).
-def imm_ldi8 : Operand<i8>
-{
- let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
+def imm_ldi8 : Operand<i8> {
+ let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
}
/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
-def imm_port5 : Operand<i8>
-{
- let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
+def imm_port5 : Operand<i8> {
+ let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
}
/// A 6-bit port number used in the `IN` instruction and friends (the
/// `FIORdA` format.
-def imm_port6 : Operand<i8>
-{
- let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
+def imm_port6 : Operand<i8> {
+ let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
}
// Addressing mode pattern reg+imm6
@@ -243,91 +228,85 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
// AsmOperand class for a pointer register.
// Used with the LD/ST family of instructions.
// See FSTLD in AVRInstrFormats.td
-def PtrRegAsmOperand : AsmOperandClass
-{
- let Name = "Reg";
-}
+def PtrRegAsmOperand : AsmOperandClass { let Name = "Reg"; }
// A special operand type for the LD/ST instructions.
// It converts the pointer register number into a two-bit field used in the
// instruction.
-def LDSTPtrReg : Operand<i16>
-{
- let MIOperandInfo = (ops PTRREGS);
- let EncoderMethod = "encodeLDSTPtrReg";
+def LDSTPtrReg : Operand<i16> {
+ let MIOperandInfo = (ops PTRREGS);
+ let EncoderMethod = "encodeLDSTPtrReg";
- let ParserMatchClass = PtrRegAsmOperand;
+ let ParserMatchClass = PtrRegAsmOperand;
}
// A special operand type for the LDD/STD instructions.
// It behaves identically to the LD/ST version, except restricts
// the pointer registers to Y and Z.
-def LDDSTDPtrReg : Operand<i16>
-{
- let MIOperandInfo = (ops PTRDISPREGS);
- let EncoderMethod = "encodeLDSTPtrReg";
+def LDDSTDPtrReg : Operand<i16> {
+ let MIOperandInfo = (ops PTRDISPREGS);
+ let EncoderMethod = "encodeLDSTPtrReg";
- let ParserMatchClass = PtrRegAsmOperand;
+ let ParserMatchClass = PtrRegAsmOperand;
}
//===----------------------------------------------------------------------===//
// AVR predicates for subtarget features
//===----------------------------------------------------------------------===//
-def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
- AssemblerPredicate<(all_of FeatureSRAM)>;
+def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
+ AssemblerPredicate<(all_of FeatureSRAM)>;
-def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
- AssemblerPredicate<(all_of FeatureJMPCALL)>;
+def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
+ AssemblerPredicate<(all_of FeatureJMPCALL)>;
-def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
- AssemblerPredicate<(all_of FeatureIJMPCALL)>;
+def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
+ AssemblerPredicate<(all_of FeatureIJMPCALL)>;
-def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
- AssemblerPredicate<(all_of FeatureEIJMPCALL)>;
+def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
+ AssemblerPredicate<(all_of FeatureEIJMPCALL)>;
-def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
- AssemblerPredicate<(all_of FeatureADDSUBIW)>;
+def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
+ AssemblerPredicate<(all_of FeatureADDSUBIW)>;
-def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
- AssemblerPredicate<(all_of FeatureSmallStack)>;
+def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
+ AssemblerPredicate<(all_of FeatureSmallStack)>;
-def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
- AssemblerPredicate<(all_of FeatureMOVW)>;
+def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
+ AssemblerPredicate<(all_of FeatureMOVW)>;
-def HasLPM : Predicate<"Subtarget->hasLPM()">,
- AssemblerPredicate<(all_of FeatureLPM)>;
+def HasLPM : Predicate<"Subtarget->hasLPM()">,
+ AssemblerPredicate<(all_of FeatureLPM)>;
-def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
- AssemblerPredicate<(all_of FeatureLPMX)>;
+def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
+ AssemblerPredicate<(all_of FeatureLPMX)>;
-def HasELPM : Predicate<"Subtarget->hasELPM()">,
- AssemblerPredicate<(all_of FeatureELPM)>;
+def HasELPM : Predicate<"Subtarget->hasELPM()">,
+ AssemblerPredicate<(all_of FeatureELPM)>;
-def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
- AssemblerPredicate<(all_of FeatureELPMX)>;
+def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
+ AssemblerPredicate<(all_of FeatureELPMX)>;
-def HasSPM : Predicate<"Subtarget->hasSPM()">,
- AssemblerPredicate<(all_of FeatureSPM)>;
+def HasSPM : Predicate<"Subtarget->hasSPM()">,
+ AssemblerPredicate<(all_of FeatureSPM)>;
-def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
- AssemblerPredicate<(all_of FeatureSPMX)>;
+def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
+ AssemblerPredicate<(all_of FeatureSPMX)>;
-def HasDES : Predicate<"Subtarget->hasDES()">,
- AssemblerPredicate<(all_of FeatureDES)>;
+def HasDES : Predicate<"Subtarget->hasDES()">,
+ AssemblerPredicate<(all_of FeatureDES)>;
-def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
- AssemblerPredicate<(all_of FeatureRMW)>;
+def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
+ AssemblerPredicate<(all_of FeatureRMW)>;
def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
- AssemblerPredicate<(all_of FeatureMultiplication)>;
+ AssemblerPredicate<(all_of FeatureMultiplication)>;
-def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
- AssemblerPredicate<(all_of FeatureBREAK)>;
+def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
+ AssemblerPredicate<(all_of FeatureBREAK)>;
def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
- AssemblerPredicate<(all_of FeatureTinyEncoding)>;
-
+ AssemblerPredicate<(all_of FeatureTinyEncoding)>;
// AVR specific condition code. These correspond to AVR_*_COND in
// AVRInstrInfo.td. They must be kept in synch.
@@ -340,7 +319,6 @@ def AVR_COND_LO : PatLeaf<(i8 5)>;
def AVR_COND_MI : PatLeaf<(i8 6)>;
def AVR_COND_PL : PatLeaf<(i8 7)>;
-
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// AVR Instruction list
@@ -352,43 +330,49 @@ def AVR_COND_PL : PatLeaf<(i8 7)>;
// pointer before prolog-epilog rewriting occurs.
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
// sub / add which can clobber SREG.
-let Defs = [SP, SREG],
-Uses = [SP] in
-{
+let Defs = [SP, SREG], Uses = [SP] in {
def ADJCALLSTACKDOWN : Pseudo<(outs),
- (ins i16imm:$amt, i16imm:$amt2),
- "#ADJCALLSTACKDOWN",
- [(AVRcallseq_start timm:$amt, timm:$amt2)]>;
+ (ins i16imm
+ : $amt, i16imm
+ : $amt2),
+ "#ADJCALLSTACKDOWN", [(AVRcallseq_start timm
+ : $amt, timm
+ : $amt2)]>;
// R31R30 is used to update SP. It is normally free because it is a
// call-clobbered register but it is necessary to set it as a def as the
// register allocator might use it in rare cases (for rematerialization, it
// seems). hasSideEffects needs to be set to true so this instruction isn't
// considered dead.
- let Defs = [R31R30],
- hasSideEffects=1 in
- def ADJCALLSTACKUP : Pseudo<(outs),
- (ins i16imm:$amt1, i16imm:$amt2),
- "#ADJCALLSTACKUP",
- [(AVRcallseq_end timm:$amt1, timm:$amt2)]>;
+ let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP
+ : Pseudo<(outs),
+ (ins i16imm
+ : $amt1, i16imm
+ : $amt2),
+ "#ADJCALLSTACKUP", [(AVRcallseq_end timm
+ : $amt1, timm
+ : $amt2)]>;
}
//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//
-let isCommutable = 1,
-Constraints = "$src = $rd",
-Defs = [SREG] in
-{
+let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
// ADD Rd, Rr
// Adds two 8-bit registers.
- def ADDRdRr : FRdRr<0b0000,
- 0b11,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "add\t$rd, $rr",
- [(set i8:$rd, (add i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ def ADDRdRr
+ : FRdRr<0b0000, 0b11,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "add\t$rd, $rr",
+ [(set i8
+ : $rd, (add i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// ADDW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values.
@@ -396,22 +380,34 @@ Defs = [SREG] in
// Expands to:
// add Rd, Rr
// adc Rd+1, Rr+1
- def ADDWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "addw\t$rd, $rr",
- [(set i16:$rd, (add i16:$src, i16:$rr)),
- (implicit SREG)]>;
+ def ADDWRdRr
+ : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "addw\t$rd, $rr",
+ [(set i16
+ : $rd, (add i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)]>;
// ADC Rd, Rr
// Adds two 8-bit registers with carry.
- let Uses = [SREG] in
- def ADCRdRr : FRdRr<0b0001,
- 0b11,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "adc\t$rd, $rr",
- [(set i8:$rd, (adde i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ let Uses = [SREG] in def ADCRdRr
+ : FRdRr<0b0001, 0b11,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "adc\t$rd, $rr",
+ [(set i8
+ : $rd, (adde i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// ADCW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values with
@@ -420,39 +416,56 @@ Defs = [SREG] in
// Expands to:
// adc Rd, Rr
// adc Rd+1, Rr+1
- let Uses = [SREG] in
- def ADCWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "adcw\t$rd, $rr",
- [(set i16:$rd, (adde i16:$src, i16:$rr)),
- (implicit SREG)]>;
+ let Uses = [SREG] in def ADCWRdRr : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "adcw\t$rd, $rr", [
+ (set i16
+ : $rd, (adde i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)
+ ]>;
// AIDW Rd, k
// Adds an immediate 6-bit value K to Rd, placing the result in Rd.
- def ADIWRdK : FWRdK<0b0,
- (outs IWREGS:$rd),
- (ins IWREGS:$src, imm_arith6:$k),
- "adiw\t$rd, $k",
- [(set i16:$rd, (add i16:$src, uimm6:$k)),
- (implicit SREG)]>,
- Requires<[HasADDSUBIW]>;
+ def ADIWRdK
+ : FWRdK<0b0,
+ (outs IWREGS
+ : $rd),
+ (ins IWREGS
+ : $src, imm_arith6
+ : $k),
+ "adiw\t$rd, $k",
+ [(set i16
+ : $rd, (add i16
+ : $src, uimm6
+ : $k)),
+ (implicit SREG)]>,
+ Requires<[HasADDSUBIW]>;
}
//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//
-let Constraints = "$src = $rd",
-Defs = [SREG] in
-{
+let Constraints = "$src = $rd", Defs = [SREG] in {
// SUB Rd, Rr
// Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
- def SUBRdRr : FRdRr<0b0001,
- 0b10,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "sub\t$rd, $rr",
- [(set i8:$rd, (sub i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ def SUBRdRr
+ : FRdRr<0b0001, 0b10,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "sub\t$rd, $rr",
+ [(set i8
+ : $rd, (sub i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// SUBW Rd+1:Rd, Rr+1:Rr
// Subtracts two 16-bit values and places the result into Rd.
@@ -460,295 +473,429 @@ Defs = [SREG] in
// Expands to:
// sub Rd, Rr
// sbc Rd+1, Rr+1
- def SUBWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "subw\t$rd, $rr",
- [(set i16:$rd, (sub i16:$src, i16:$rr)),
- (implicit SREG)]>;
-
- def SUBIRdK : FRdK<0b0101,
- (outs LD8:$rd),
- (ins LD8:$src, imm_ldi8:$k),
- "subi\t$rd, $k",
- [(set i8:$rd, (sub i8:$src, imm:$k)),
- (implicit SREG)]>;
+ def SUBWRdRr
+ : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "subw\t$rd, $rr",
+ [(set i16
+ : $rd, (sub i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)]>;
+
+ def SUBIRdK
+ : FRdK<0b0101,
+ (outs LD8
+ : $rd),
+ (ins LD8
+ : $src, imm_ldi8
+ : $k),
+ "subi\t$rd, $k",
+ [(set i8
+ : $rd, (sub i8
+ : $src, imm
+ : $k)),
+ (implicit SREG)]>;
// SUBIW Rd+1:Rd, K+1:K
//
// Expands to:
// subi Rd, K
// sbci Rd+1, K+1
- def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
- (ins DLDREGS:$src, i16imm:$rr),
- "subiw\t$rd, $rr",
- [(set i16:$rd, (sub i16:$src, imm:$rr)),
- (implicit SREG)]>;
-
- def SBIWRdK : FWRdK<0b1,
- (outs IWREGS:$rd),
- (ins IWREGS:$src, imm_arith6:$k),
- "sbiw\t$rd, $k",
- [(set i16:$rd, (sub i16:$src, uimm6:$k)),
- (implicit SREG)]>,
- Requires<[HasADDSUBIW]>;
+ def SUBIWRdK
+ : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DLDREGS
+ : $src, i16imm
+ : $rr),
+ "subiw\t$rd, $rr",
+ [(set i16
+ : $rd, (sub i16
+ : $src, imm
+ : $rr)),
+ (implicit SREG)]>;
+
+ def SBIWRdK
+ : FWRdK<0b1,
+ (outs IWREGS
+ : $rd),
+ (ins IWREGS
+ : $src, imm_arith6
+ : $k),
+ "sbiw\t$rd, $k",
+ [(set i16
+ : $rd, (sub i16
+ : $src, uimm6
+ : $k)),
+ (implicit SREG)]>,
+ Requires<[HasADDSUBIW]>;
// Subtract with carry operations which must read the carry flag in SREG.
- let Uses = [SREG] in
- {
- def SBCRdRr : FRdRr<0b0000,
- 0b10,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "sbc\t$rd, $rr",
- [(set i8:$rd, (sube i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ let Uses = [SREG] in {
+ def SBCRdRr
+ : FRdRr<0b0000, 0b10,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "sbc\t$rd, $rr",
+ [(set i8
+ : $rd, (sube i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// SBCW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// sbc Rd, Rr
// sbc Rd+1, Rr+1
- def SBCWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "sbcw\t$rd, $rr",
- [(set i16:$rd, (sube i16:$src, i16:$rr)),
- (implicit SREG)]>;
-
- def SBCIRdK : FRdK<0b0100,
- (outs LD8:$rd),
- (ins LD8:$src, imm_ldi8:$k),
- "sbci\t$rd, $k",
- [(set i8:$rd, (sube i8:$src, imm:$k)),
- (implicit SREG)]>;
+ def SBCWRdRr : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "sbcw\t$rd, $rr", [
+ (set i16
+ : $rd, (sube i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)
+ ]>;
+
+ def SBCIRdK
+ : FRdK<0b0100,
+ (outs LD8
+ : $rd),
+ (ins LD8
+ : $src, imm_ldi8
+ : $k),
+ "sbci\t$rd, $k",
+ [(set i8
+ : $rd, (sube i8
+ : $src, imm
+ : $k)),
+ (implicit SREG)]>;
// SBCIW Rd+1:Rd, K+1:K
// sbci Rd, K
// sbci Rd+1, K+1
- def SBCIWRdK : Pseudo<(outs DLDREGS:$rd),
- (ins DLDREGS:$src, i16imm:$rr),
- "sbciw\t$rd, $rr",
- [(set i16:$rd, (sube i16:$src, imm:$rr)),
- (implicit SREG)]>;
+ def SBCIWRdK : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DLDREGS
+ : $src, i16imm
+ : $rr),
+ "sbciw\t$rd, $rr", [
+ (set i16
+ : $rd, (sube i16
+ : $src, imm
+ : $rr)),
+ (implicit SREG)
+ ]>;
}
}
//===----------------------------------------------------------------------===//
// Increment and Decrement
//===----------------------------------------------------------------------===//
-let Constraints = "$src = $rd",
-Defs = [SREG] in
-{
- def INCRd : FRd<0b1001,
- 0b0100011,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "inc\t$rd",
- [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>;
-
- def DECRd : FRd<0b1001,
- 0b0101010,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "dec\t$rd",
- [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>;
+let Constraints = "$src = $rd", Defs = [SREG] in {
+ def INCRd
+ : FRd<0b1001, 0b0100011,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "inc\t$rd", [(set i8
+ : $rd, (add i8
+ : $src, 1)),
+ (implicit SREG)]>;
+
+ def DECRd
+ : FRd<0b1001, 0b0101010,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "dec\t$rd", [(set i8
+ : $rd, (add i8
+ : $src, -1)),
+ (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// Multiplication
//===----------------------------------------------------------------------===//
-let isCommutable = 1,
-Defs = [R1, R0, SREG] in
-{
+let isCommutable = 1, Defs = [R1, R0, SREG] in {
// MUL Rd, Rr
// Multiplies Rd by Rr and places the result into R1:R0.
let usesCustomInserter = 1 in {
- def MULRdRr : FRdRr<0b1001, 0b11,
- (outs),
- (ins GPR8:$lhs, GPR8:$rhs),
+ def MULRdRr : FRdRr<0b1001, 0b11, (outs),
+ (ins GPR8
+ : $lhs, GPR8
+ : $rhs),
"mul\t$lhs, $rhs",
[/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
- Requires<[SupportsMultiplication]>;
+ Requires<[SupportsMultiplication]>;
- def MULSRdRr : FMUL2RdRr<0,
- (outs),
- (ins LD8:$lhs, LD8:$rhs),
- "muls\t$lhs, $rhs",
- []>,
+ def MULSRdRr : FMUL2RdRr<0, (outs),
+ (ins LD8
+ : $lhs, LD8
+ : $rhs),
+ "muls\t$lhs, $rhs", []>,
Requires<[SupportsMultiplication]>;
}
- def MULSURdRr : FMUL2RdRr<1,
- (outs),
- (ins LD8lo:$lhs, LD8lo:$rhs),
- "mulsu\t$lhs, $rhs",
- []>,
+ def MULSURdRr : FMUL2RdRr<1, (outs),
+ (ins LD8lo
+ : $lhs, LD8lo
+ : $rhs),
+ "mulsu\t$lhs, $rhs", []>,
Requires<[SupportsMultiplication]>;
- def FMUL : FFMULRdRr<0b01,
- (outs),
- (ins LD8lo:$lhs, LD8lo:$rhs),
- "fmul\t$lhs, $rhs",
- []>,
+ def FMUL : FFMULRdRr<0b01, (outs),
+ (ins LD8lo
+ : $lhs, LD8lo
+ : $rhs),
+ "fmul\t$lhs, $rhs", []>,
Requires<[SupportsMultiplication]>;
- def FMULS : FFMULRdRr<0b10,
- (outs),
- (ins LD8lo:$lhs, LD8lo:$rhs),
- "fmuls\t$lhs, $rhs",
- []>,
+ def FMULS : FFMULRdRr<0b10, (outs),
+ (ins LD8lo
+ : $lhs, LD8lo
+ : $rhs),
+ "fmuls\t$lhs, $rhs", []>,
Requires<[SupportsMultiplication]>;
- def FMULSU : FFMULRdRr<0b11,
- (outs),
- (ins LD8lo:$lhs, LD8lo:$rhs),
- "fmulsu\t$lhs, $rhs",
- []>,
+ def FMULSU : FFMULRdRr<0b11, (outs),
+ (ins LD8lo
+ : $lhs, LD8lo
+ : $rhs),
+ "fmulsu\t$lhs, $rhs", []>,
Requires<[SupportsMultiplication]>;
}
-let Defs = [R15, R14, R13, R12, R11, R10, R9,
- R8, R7, R6, R5, R4, R3, R2, R1, R0] in
-def DESK : FDES<(outs),
- (ins i8imm:$k),
- "des\t$k",
- []>,
- Requires<[HasDES]>;
+let Defs =
+ [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1,
+ R0] in def DESK : FDES<(outs),
+ (ins i8imm
+ : $k),
+ "des\t$k", []>,
+ Requires<[HasDES]>;
//===----------------------------------------------------------------------===//
// Logic
//===----------------------------------------------------------------------===//
-let Constraints = "$src = $rd",
-Defs = [SREG] in
-{
+let Constraints = "$src = $rd", Defs = [SREG] in {
// Register-Register logic instructions (which have the
// property of commutativity).
- let isCommutable = 1 in
- {
- def ANDRdRr : FRdRr<0b0010,
- 0b00,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "and\t$rd, $rr",
- [(set i8:$rd, (and i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ let isCommutable = 1 in {
+ def ANDRdRr
+ : FRdRr<0b0010, 0b00,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "and\t$rd, $rr",
+ [(set i8
+ : $rd, (and i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// ANDW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// and Rd, Rr
// and Rd+1, Rr+1
- def ANDWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "andw\t$rd, $rr",
- [(set i16:$rd, (and i16:$src, i16:$rr)),
- (implicit SREG)]>;
-
- def ORRdRr : FRdRr<0b0010,
- 0b10,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "or\t$rd, $rr",
- [(set i8:$rd, (or i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ def ANDWRdRr : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "andw\t$rd, $rr", [
+ (set i16
+ : $rd, (and i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)
+ ]>;
+
+ def ORRdRr
+ : FRdRr<0b0010, 0b10,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "or\t$rd, $rr",
+ [(set i8
+ : $rd, (or i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// ORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// or Rd, Rr
// or Rd+1, Rr+1
- def ORWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "orw\t$rd, $rr",
- [(set i16:$rd, (or i16:$src, i16:$rr)),
- (implicit SREG)]>;
-
- def EORRdRr : FRdRr<0b0010,
- 0b01,
- (outs GPR8:$rd),
- (ins GPR8:$src, GPR8:$rr),
- "eor\t$rd, $rr",
- [(set i8:$rd, (xor i8:$src, i8:$rr)),
- (implicit SREG)]>;
+ def ORWRdRr : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "orw\t$rd, $rr", [
+ (set i16
+ : $rd, (or i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)
+ ]>;
+
+ def EORRdRr
+ : FRdRr<0b0010, 0b01,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, GPR8
+ : $rr),
+ "eor\t$rd, $rr",
+ [(set i8
+ : $rd, (xor i8
+ : $src, i8
+ : $rr)),
+ (implicit SREG)]>;
// EORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// eor Rd, Rr
// eor Rd+1, Rr+1
- def EORWRdRr : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src, DREGS:$rr),
- "eorw\t$rd, $rr",
- [(set i16:$rd, (xor i16:$src, i16:$rr)),
- (implicit SREG)]>;
+ def EORWRdRr : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src, DREGS
+ : $rr),
+ "eorw\t$rd, $rr", [
+ (set i16
+ : $rd, (xor i16
+ : $src, i16
+ : $rr)),
+ (implicit SREG)
+ ]>;
}
- def ANDIRdK : FRdK<0b0111,
- (outs LD8:$rd),
- (ins LD8:$src, imm_ldi8:$k),
- "andi\t$rd, $k",
- [(set i8:$rd, (and i8:$src, imm:$k)),
- (implicit SREG)]>;
+ def ANDIRdK
+ : FRdK<0b0111,
+ (outs LD8
+ : $rd),
+ (ins LD8
+ : $src, imm_ldi8
+ : $k),
+ "andi\t$rd, $k",
+ [(set i8
+ : $rd, (and i8
+ : $src, imm
+ : $k)),
+ (implicit SREG)]>;
// ANDI Rd+1:Rd, K+1:K
//
// Expands to:
// andi Rd, K
// andi Rd+1, K+1
- def ANDIWRdK : Pseudo<(outs DLDREGS:$rd),
- (ins DLDREGS:$src, i16imm:$k),
- "andiw\t$rd, $k",
- [(set i16:$rd, (and i16:$src, imm:$k)),
- (implicit SREG)]>;
-
- def ORIRdK : FRdK<0b0110,
- (outs LD8:$rd),
- (ins LD8:$src, imm_ldi8:$k),
- "ori\t$rd, $k",
- [(set i8:$rd, (or i8:$src, imm:$k)),
- (implicit SREG)]>;
+ def ANDIWRdK
+ : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DLDREGS
+ : $src, i16imm
+ : $k),
+ "andiw\t$rd, $k",
+ [(set i16
+ : $rd, (and i16
+ : $src, imm
+ : $k)),
+ (implicit SREG)]>;
+
+ def ORIRdK
+ : FRdK<0b0110,
+ (outs LD8
+ : $rd),
+ (ins LD8
+ : $src, imm_ldi8
+ : $k),
+ "ori\t$rd, $k",
+ [(set i8
+ : $rd, (or i8
+ : $src, imm
+ : $k)),
+ (implicit SREG)]>;
// ORIW Rd+1:Rd, K+1,K
//
// Expands to:
// ori Rd, K
// ori Rd+1, K+1
- def ORIWRdK : Pseudo<(outs DLDREGS:$rd),
- (ins DLDREGS:$src, i16imm:$rr),
- "oriw\t$rd, $rr",
- [(set i16:$rd, (or i16:$src, imm:$rr)),
- (implicit SREG)]>;
+ def ORIWRdK
+ : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DLDREGS
+ : $src, i16imm
+ : $rr),
+ "oriw\t$rd, $rr",
+ [(set i16
+ : $rd, (or i16
+ : $src, imm
+ : $rr)),
+ (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// One's/Two's Complement
//===----------------------------------------------------------------------===//
-let Constraints = "$src = $rd",
-Defs = [SREG] in
-{
- def COMRd : FRd<0b1001,
- 0b0100000,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "com\t$rd",
- [(set i8:$rd, (not i8:$src)), (implicit SREG)]>;
+let Constraints = "$src = $rd", Defs = [SREG] in {
+ def COMRd
+ : FRd<0b1001, 0b0100000,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "com\t$rd", [(set i8
+ : $rd, (not i8
+ : $src)),
+ (implicit SREG)]>;
// COMW Rd+1:Rd
//
// Expands to:
// com Rd
// com Rd+1
- def COMWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
+ def COMWRd : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
"comw\t$rd",
- [(set i16:$rd, (not i16:$src)), (implicit SREG)]>;
+ [(set i16
+ : $rd, (not i16
+ : $src)),
+ (implicit SREG)]>;
- def NEGRd : FRd<0b1001,
- 0b0100001,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "neg\t$rd",
- [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
+ def NEGRd
+ : FRd<0b1001, 0b0100001,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "neg\t$rd", [(set i8
+ : $rd, (ineg i8
+ : $src)),
+ (implicit SREG)]>;
// NEGW Rd+1:Rd
//
@@ -756,155 +903,126 @@ Defs = [SREG] in
// neg Rd+1
// neg Rd
// sbc Rd+1, r1
- def NEGWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
+ def NEGWRd : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
"negw\t$rd",
- [(set i16:$rd, (ineg i16:$src)), (implicit SREG)]>;
+ [(set i16
+ : $rd, (ineg i16
+ : $src)),
+ (implicit SREG)]>;
}
// TST Rd
// Test for zero of minus.
// This operation is identical to a `Rd AND Rd`.
-def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;
+def : InstAlias<"tst\t$rd", (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
// SBR Rd, K
//
// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
// same everything.
def : InstAlias<"sbr\t$rd, $k",
- (ORIRdK LD8:$rd, imm_ldi8:$k),
+ (ORIRdK LD8
+ : $rd, imm_ldi8
+ : $k),
/* Disable display, so we don't override ORI */ 0>;
//===----------------------------------------------------------------------===//
// Jump instructions
//===----------------------------------------------------------------------===//
-let isBarrier = 1,
-isBranch = 1,
-isTerminator = 1 in
-{
- def RJMPk : FBRk<0,
- (outs),
- (ins brtarget_13:$target),
- "rjmp\t$target",
- [(br bb:$target)]>;
+let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
+ def RJMPk : FBRk<0, (outs),
+ (ins brtarget_13
+ : $target),
+ "rjmp\t$target", [(br bb
+ : $target)]>;
let isIndirectBranch = 1,
- Uses = [R31R30] in
- def IJMP : F16<0b1001010000001001,
- (outs),
- (ins),
- "ijmp",
- []>,
- Requires<[HasIJMPCALL]>;
+ Uses = [R31R30] in def IJMP
+ : F16<0b1001010000001001, (outs), (ins), "ijmp", []>,
+ Requires<[HasIJMPCALL]>;
let isIndirectBranch = 1,
- Uses = [R31R30] in
- def EIJMP : F16<0b1001010000011001,
- (outs),
- (ins),
- "eijmp",
- []>,
- Requires<[HasEIJMPCALL]>;
-
- def JMPk : F32BRk<0b110,
- (outs),
- (ins call_target:$k),
- "jmp\t$k",
- []>,
+ Uses = [R31R30] in def EIJMP
+ : F16<0b1001010000011001, (outs), (ins), "eijmp", []>,
+ Requires<[HasEIJMPCALL]>;
+
+ def JMPk : F32BRk<0b110, (outs),
+ (ins call_target
+ : $k),
+ "jmp\t$k", []>,
Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Call instructions
//===----------------------------------------------------------------------===//
-let isCall = 1 in
-{
+let isCall = 1 in {
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
- let Uses = [SP] in
- def RCALLk : FBRk<1,
- (outs),
- (ins brtarget_13:$target),
- "rcall\t$target",
- []>;
+ let Uses = [SP] in def RCALLk : FBRk<1, (outs),
+ (ins brtarget_13
+ : $target),
+ "rcall\t$target", []>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
- let Uses = [SP, R31R30] in
- def ICALL : F16<0b1001010100001001,
- (outs),
- (ins variable_ops),
- "icall",
- []>,
- Requires<[HasIJMPCALL]>;
+ let Uses = [SP, R31R30] in def ICALL
+ : F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>,
+ Requires<[HasIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
- let Uses = [SP, R31R30] in
- def EICALL : F16<0b1001010100011001,
- (outs),
- (ins variable_ops),
- "eicall",
- []>,
- Requires<[HasEIJMPCALL]>;
+ let Uses = [SP, R31R30] in def EICALL
+ : F16<0b1001010100011001, (outs), (ins variable_ops), "eicall", []>,
+ Requires<[HasEIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
//
- //:TODO: the imm field can be either 16 or 22 bits in devices with more
+ //: TODO: the imm field can be either 16 or 22 bits in devices with more
// than 64k of ROM, fix it once we support the largest devices.
- let Uses = [SP] in
- def CALLk : F32BRk<0b111,
- (outs),
- (ins call_target:$k),
- "call\t$k",
- [(AVRcall imm:$k)]>,
- Requires<[HasJMPCALL]>;
+ let Uses = [SP] in def CALLk : F32BRk<0b111, (outs),
+ (ins call_target
+ : $k),
+ "call\t$k", [(AVRcall imm
+ : $k)]>,
+ Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Return instructions.
//===----------------------------------------------------------------------===//
-let isTerminator = 1,
-isReturn = 1,
-isBarrier = 1 in
-{
- def RET : F16<0b1001010100001000,
- (outs),
- (ins),
- "ret",
- [(AVRretflag)]>;
-
- def RETI : F16<0b1001010100011000,
- (outs),
- (ins),
- "reti",
- [(AVRretiflag)]>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
+ def RET : F16<0b1001010100001000, (outs), (ins), "ret", [(AVRretflag)]>;
+
+ def RETI : F16<0b1001010100011000, (outs), (ins), "reti", [(AVRretiflag)]>;
}
//===----------------------------------------------------------------------===//
// Compare operations.
//===----------------------------------------------------------------------===//
-let Defs = [SREG] in
-{
+let Defs = [SREG] in {
// CPSE Rd, Rr
// Compare Rd and Rr, skipping the next instruction if they are equal.
- let isBarrier = 1,
- isBranch = 1,
- isTerminator = 1 in
- def CPSE : FRdRr<0b0001,
- 0b00,
- (outs),
- (ins GPR8:$rd, GPR8:$rr),
- "cpse\t$rd, $rr",
- []>;
-
- def CPRdRr : FRdRr<0b0001,
- 0b01,
- (outs),
- (ins GPR8:$rd, GPR8:$rr),
- "cp\t$rd, $rr",
- [(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>;
+ let isBarrier = 1, isBranch = 1,
+ isTerminator = 1 in def CPSE : FRdRr<0b0001, 0b00, (outs),
+ (ins GPR8
+ : $rd, GPR8
+ : $rr),
+ "cpse\t$rd, $rr", []>;
+
+ def CPRdRr
+ : FRdRr<0b0001, 0b01, (outs),
+ (ins GPR8
+ : $rd, GPR8
+ : $rr),
+ "cp\t$rd, $rr", [(AVRcmp i8
+ : $rd, i8
+ : $rr),
+ (implicit SREG)]>;
// CPW Rd+1:Rd, Rr+1:Rr
//
@@ -912,251 +1030,256 @@ let Defs = [SREG] in
// cp Rd, Rr
// cpc Rd+1, Rr+1
def CPWRdRr : Pseudo<(outs),
- (ins DREGS:$src, DREGS:$src2),
+ (ins DREGS
+ : $src, DREGS
+ : $src2),
"cpw\t$src, $src2",
- [(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>;
+ [(AVRcmp i16
+ : $src, i16
+ : $src2),
+ (implicit SREG)]>;
- let Uses = [SREG] in
- def CPCRdRr : FRdRr<0b0000,
- 0b01,
- (outs),
- (ins GPR8:$rd, GPR8:$rr),
- "cpc\t$rd, $rr",
- [(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>;
+ let Uses = [SREG] in def CPCRdRr
+ : FRdRr<0b0000, 0b01, (outs),
+ (ins GPR8
+ : $rd, GPR8
+ : $rr),
+ "cpc\t$rd, $rr", [(AVRcmpc i8
+ : $rd, i8
+ : $rr),
+ (implicit SREG)]>;
// CPCW Rd+1:Rd. Rr+1:Rr
//
// Expands to:
// cpc Rd, Rr
// cpc Rd+1, Rr+1
- let Uses = [SREG] in
- def CPCWRdRr : Pseudo<(outs),
- (ins DREGS:$src, DREGS:$src2),
- "cpcw\t$src, $src2",
- [(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>;
+ let Uses = [SREG] in def CPCWRdRr
+ : Pseudo<(outs),
+ (ins DREGS
+ : $src, DREGS
+ : $src2),
+ "cpcw\t$src, $src2",
+ [(AVRcmpc i16
+ : $src, i16
+ : $src2),
+ (implicit SREG)]>;
// CPI Rd, K
// Compares a register with an 8 bit immediate.
- def CPIRdK : FRdK<0b0011,
- (outs),
- (ins LD8:$rd, imm_ldi8:$k),
- "cpi\t$rd, $k",
- [(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>;
+ def CPIRdK
+ : FRdK<0b0011, (outs),
+ (ins LD8
+ : $rd, imm_ldi8
+ : $k),
+ "cpi\t$rd, $k", [(AVRcmp i8
+ : $rd, imm
+ : $k),
+ (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// Register conditional skipping/branching operations.
//===----------------------------------------------------------------------===//
-let isBranch = 1,
-isTerminator = 1 in
-{
+let isBranch = 1, isTerminator = 1 in {
// Conditional skipping on GPR register bits, and
// conditional skipping on IO register bits.
- let isBarrier = 1 in
- {
- def SBRCRrB : FRdB<0b10,
- (outs),
- (ins GPR8:$rr, i8imm:$b),
- "sbrc\t$rr, $b",
- []>;
-
- def SBRSRrB : FRdB<0b11,
- (outs),
- (ins GPR8:$rr, i8imm:$b),
- "sbrs\t$rr, $b",
- []>;
-
- def SBICAb : FIOBIT<0b01,
- (outs),
- (ins imm_port5:$a, i8imm:$b),
- "sbic\t$a, $b",
- []>;
-
- def SBISAb : FIOBIT<0b11,
- (outs),
- (ins imm_port5:$a, i8imm:$b),
- "sbis\t$a, $b",
- []>;
+ let isBarrier = 1 in {
+ def SBRCRrB : FRdB<0b10, (outs),
+ (ins GPR8
+ : $rr, i8imm
+ : $b),
+ "sbrc\t$rr, $b", []>;
+
+ def SBRSRrB : FRdB<0b11, (outs),
+ (ins GPR8
+ : $rr, i8imm
+ : $b),
+ "sbrs\t$rr, $b", []>;
+
+ def SBICAb : FIOBIT<0b01, (outs),
+ (ins imm_port5
+ : $a, i8imm
+ : $b),
+ "sbic\t$a, $b", []>;
+
+ def SBISAb : FIOBIT<0b11, (outs),
+ (ins imm_port5
+ : $a, i8imm
+ : $b),
+ "sbis\t$a, $b", []>;
}
// Relative branches on status flag bits.
- let Uses = [SREG] in
- {
+ let Uses = [SREG] in {
// BRBS s, k
// Branch if `s` flag in status register is set.
- def BRBSsk : FSK<0,
- (outs),
- (ins i8imm:$s, relbrtarget_7:$k),
- "brbs\t$s, $k",
- []>;
+ def BRBSsk : FSK<0, (outs),
+ (ins i8imm
+ : $s, relbrtarget_7
+ : $k),
+ "brbs\t$s, $k", []>;
// BRBC s, k
// Branch if `s` flag in status register is clear.
- def BRBCsk : FSK<1,
- (outs),
- (ins i8imm:$s, relbrtarget_7:$k),
- "brbc\t$s, $k",
- []>;
+ def BRBCsk : FSK<1, (outs),
+ (ins i8imm
+ : $s, relbrtarget_7
+ : $k),
+ "brbc\t$s, $k", []>;
}
}
-
// BRCS k
// Branch if carry flag is set
-def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7:$k)>;
+def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7 : $k)>;
// BRCC k
// Branch if carry flag is clear
-def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7:$k)>;
+def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7 : $k)>;
// BRHS k
// Branch if half carry flag is set
-def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7:$k)>;
+def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7 : $k)>;
// BRHC k
// Branch if half carry flag is clear
-def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7:$k)>;
+def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7 : $k)>;
// BRTS k
// Branch if the T flag is set
-def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7:$k)>;
+def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7 : $k)>;
// BRTC k
// Branch if the T flag is clear
-def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7:$k)>;
+def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7 : $k)>;
// BRVS k
// Branch if the overflow flag is set
-def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7:$k)>;
+def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7 : $k)>;
// BRVC k
// Branch if the overflow flag is clear
-def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7:$k)>;
+def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7 : $k)>;
// BRIE k
// Branch if the global interrupt flag is enabled
-def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7:$k)>;
+def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7 : $k)>;
// BRID k
// Branch if the global interrupt flag is disabled
-def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7:$k)>;
+def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>;
//===----------------------------------------------------------------------===//
// PC-relative conditional branches
//===----------------------------------------------------------------------===//
// Based on status register. We cannot simplify these into instruction aliases
// because we also need to be able to specify a pattern to match for ISel.
-let isBranch = 1,
-isTerminator = 1,
-Uses = [SREG] in
-{
- def BREQk : FBRsk<0,
- 0b001,
- (outs),
- (ins relbrtarget_7:$target),
- "breq\t$target",
- [(AVRbrcond bb:$target, AVR_COND_EQ)]>;
-
- def BRNEk : FBRsk<1,
- 0b001,
- (outs),
- (ins relbrtarget_7:$target),
- "brne\t$target",
- [(AVRbrcond bb:$target, AVR_COND_NE)]>;
-
-
- def BRSHk : FBRsk<1,
- 0b000,
- (outs),
- (ins relbrtarget_7:$target),
- "brsh\t$target",
- [(AVRbrcond bb:$target, AVR_COND_SH)]>;
-
- def BRLOk : FBRsk<0,
- 0b000,
- (outs),
- (ins relbrtarget_7:$target),
- "brlo\t$target",
- [(AVRbrcond bb:$target, AVR_COND_LO)]>;
-
- def BRMIk : FBRsk<0,
- 0b010,
- (outs),
- (ins relbrtarget_7:$target),
- "brmi\t$target",
- [(AVRbrcond bb:$target, AVR_COND_MI)]>;
-
- def BRPLk : FBRsk<1,
- 0b010,
- (outs),
- (ins relbrtarget_7:$target),
- "brpl\t$target",
- [(AVRbrcond bb:$target, AVR_COND_PL)]>;
-
- def BRGEk : FBRsk<1,
- 0b100,
- (outs),
- (ins relbrtarget_7:$target),
- "brge\t$target",
- [(AVRbrcond bb:$target, AVR_COND_GE)]>;
-
- def BRLTk : FBRsk<0,
- 0b100,
- (outs),
- (ins relbrtarget_7:$target),
- "brlt\t$target",
- [(AVRbrcond bb:$target, AVR_COND_LT)]>;
+let isBranch = 1, isTerminator = 1, Uses = [SREG] in {
+ def BREQk : FBRsk<0, 0b001, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "breq\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_EQ)]>;
+
+ def BRNEk : FBRsk<1, 0b001, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brne\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_NE)]>;
+
+ def BRSHk : FBRsk<1, 0b000, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brsh\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_SH)]>;
+
+ def BRLOk : FBRsk<0, 0b000, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brlo\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_LO)]>;
+
+ def BRMIk : FBRsk<0, 0b010, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brmi\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_MI)]>;
+
+ def BRPLk : FBRsk<1, 0b010, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brpl\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_PL)]>;
+
+ def BRGEk : FBRsk<1, 0b100, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brge\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_GE)]>;
+
+ def BRLTk : FBRsk<0, 0b100, (outs),
+ (ins relbrtarget_7
+ : $target),
+ "brlt\t$target", [(AVRbrcond bb
+ : $target, AVR_COND_LT)]>;
}
//===----------------------------------------------------------------------===//
// Data transfer instructions
//===----------------------------------------------------------------------===//
// 8 and 16-bit register move instructions.
-let hasSideEffects = 0 in
-{
- def MOVRdRr : FRdRr<0b0010,
- 0b11,
- (outs GPR8:$rd),
- (ins GPR8:$rr),
- "mov\t$rd, $rr",
- []>;
-
- def MOVWRdRr : FMOVWRdRr<(outs DREGS:$dst),
- (ins DREGS:$src),
- "movw\t$dst, $src",
- []>,
+let hasSideEffects = 0 in {
+ def MOVRdRr : FRdRr<0b0010, 0b11,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $rr),
+ "mov\t$rd, $rr", []>;
+
+ def MOVWRdRr : FMOVWRdRr<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src),
+ "movw\t$dst, $src", []>,
Requires<[HasMOVW]>;
}
// Load immediate values into registers.
-let isReMaterializable = 1 in
-{
+let isReMaterializable = 1 in {
def LDIRdK : FRdK<0b1110,
- (outs LD8:$rd),
- (ins imm_ldi8:$k),
- "ldi\t$rd, $k",
- [(set i8:$rd, imm:$k)]>;
+ (outs LD8
+ : $rd),
+ (ins imm_ldi8
+ : $k),
+ "ldi\t$rd, $k", [(set i8
+ : $rd, imm
+ : $k)]>;
// LDIW Rd+1:Rd, K+1:K
//
// Expands to:
// ldi Rd, K
// ldi Rd+1, K+1
- def LDIWRdK : Pseudo<(outs DLDREGS:$dst),
- (ins i16imm:$src),
- "ldiw\t$dst, $src",
- [(set i16:$dst, imm:$src)]>;
+ def LDIWRdK : Pseudo<(outs DLDREGS
+ : $dst),
+ (ins i16imm
+ : $src),
+ "ldiw\t$dst, $src", [(set i16
+ : $dst, imm
+ : $src)]>;
}
// Load from data space into register.
-let canFoldAsLoad = 1,
-isReMaterializable = 1 in
-{
+let canFoldAsLoad = 1, isReMaterializable = 1 in {
def LDSRdK : F32DM<0b0,
- (outs GPR8:$rd),
- (ins imm16:$k),
- "lds\t$rd, $k",
- [(set i8:$rd, (load imm:$k))]>,
+ (outs GPR8
+ : $rd),
+ (ins imm16
+ : $k),
+ "lds\t$rd, $k", [(set i8
+ : $rd, (load imm
+ : $k))]>,
Requires<[HasSRAM]>;
// LDSW Rd+1:Rd, K+1:K
@@ -1164,23 +1287,26 @@ isReMaterializable = 1 in
// Expands to:
// lds Rd, (K+1:K)
// lds Rd+1 (K+1:K) + 1
- def LDSWRdK : Pseudo<(outs DREGS:$dst),
- (ins i16imm:$src),
- "ldsw\t$dst, $src",
- [(set i16:$dst, (load imm:$src))]>,
+ def LDSWRdK : Pseudo<(outs DREGS
+ : $dst),
+ (ins i16imm
+ : $src),
+ "ldsw\t$dst, $src", [(set i16
+ : $dst, (load imm
+ : $src))]>,
Requires<[HasSRAM]>;
}
// Indirect loads.
-let canFoldAsLoad = 1,
-isReMaterializable = 1 in
-{
- def LDRdPtr : FSTLD<0,
- 0b00,
- (outs GPR8:$reg),
- (ins LDSTPtrReg:$ptrreg),
- "ld\t$reg, $ptrreg",
- [(set GPR8:$reg, (load i16:$ptrreg))]>,
+let canFoldAsLoad = 1, isReMaterializable = 1 in {
+ def LDRdPtr : FSTLD<0, 0b00,
+ (outs GPR8
+ : $reg),
+ (ins LDSTPtrReg
+ : $ptrreg),
+ "ld\t$reg, $ptrreg", [(set GPR8
+ : $reg, (load i16
+ : $ptrreg))]>,
Requires<[HasSRAM]>;
// LDW Rd+1:Rd, P
@@ -1188,43 +1314,48 @@ isReMaterializable = 1 in
// Expands to:
// ld Rd, P
// ldd Rd+1, P+1
- let Constraints = "@earlyclobber $reg" in
- def LDWRdPtr : Pseudo<(outs DREGS:$reg),
- (ins PTRDISPREGS:$ptrreg),
- "ldw\t$reg, $ptrreg",
- [(set i16:$reg, (load i16:$ptrreg))]>,
- Requires<[HasSRAM]>;
+ let Constraints = "@earlyclobber $reg" in def LDWRdPtr
+ : Pseudo<(outs DREGS
+ : $reg),
+ (ins PTRDISPREGS
+ : $ptrreg),
+ "ldw\t$reg, $ptrreg", [(set i16
+ : $reg, (load i16
+ : $ptrreg))]>,
+ Requires<[HasSRAM]>;
}
// Indirect loads (with postincrement or predecrement).
-let mayLoad = 1,
-hasSideEffects = 0,
-Constraints = "$ptrreg = $base_wb, at earlyclobber $reg" in
-{
- def LDRdPtrPi : FSTLD<0,
- 0b01,
- (outs GPR8:$reg, PTRREGS:$base_wb),
- (ins LDSTPtrReg:$ptrreg),
- "ld\t$reg, $ptrreg+",
- []>,
+let mayLoad = 1, hasSideEffects = 0,
+ Constraints = "$ptrreg = $base_wb, at earlyclobber $reg" in {
+ def LDRdPtrPi : FSTLD<0, 0b01,
+ (outs GPR8
+ : $reg, PTRREGS
+ : $base_wb),
+ (ins LDSTPtrReg
+ : $ptrreg),
+ "ld\t$reg, $ptrreg+", []>,
Requires<[HasSRAM]>;
// LDW Rd+1:Rd, P+
// Expands to:
// ld Rd, P+
// ld Rd+1, P+
- def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
- (ins PTRREGS:$ptrreg),
- "ldw\t$reg, $ptrreg+",
- []>,
+ def LDWRdPtrPi : Pseudo<(outs DREGS
+ : $reg, PTRREGS
+ : $base_wb),
+ (ins PTRREGS
+ : $ptrreg),
+ "ldw\t$reg, $ptrreg+", []>,
Requires<[HasSRAM]>;
- def LDRdPtrPd : FSTLD<0,
- 0b10,
- (outs GPR8:$reg, PTRREGS:$base_wb),
- (ins LDSTPtrReg:$ptrreg),
- "ld\t$reg, -$ptrreg",
- []>,
+ def LDRdPtrPd : FSTLD<0, 0b10,
+ (outs GPR8
+ : $reg, PTRREGS
+ : $base_wb),
+ (ins LDSTPtrReg
+ : $ptrreg),
+ "ld\t$reg, -$ptrreg", []>,
Requires<[HasSRAM]>;
// LDW Rd+1:Rd, -P
@@ -1232,36 +1363,42 @@ Constraints = "$ptrreg = $base_wb, at earlyclobber $reg" in
// Expands to:
// ld Rd+1, -P
// ld Rd, -P
- def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),
- (ins PTRREGS:$ptrreg),
- "ldw\t$reg, -$ptrreg",
- []>,
+ def LDWRdPtrPd : Pseudo<(outs DREGS
+ : $reg, PTRREGS
+ : $base_wb),
+ (ins PTRREGS
+ : $ptrreg),
+ "ldw\t$reg, -$ptrreg", []>,
Requires<[HasSRAM]>;
}
// Load indirect with displacement operations.
-let canFoldAsLoad = 1,
-isReMaterializable = 1 in
-{
- let Constraints = "@earlyclobber $reg" in
- def LDDRdPtrQ : FSTDLDD<0,
- (outs GPR8:$reg),
- (ins memri:$memri),
- "ldd\t$reg, $memri",
- [(set i8:$reg, (load addr:$memri))]>,
- Requires<[HasSRAM]>;
+let canFoldAsLoad = 1, isReMaterializable = 1 in {
+ let Constraints = "@earlyclobber $reg" in def LDDRdPtrQ
+ : FSTDLDD<0,
+ (outs GPR8
+ : $reg),
+ (ins memri
+ : $memri),
+ "ldd\t$reg, $memri", [(set i8
+ : $reg, (load addr
+ : $memri))]>,
+ Requires<[HasSRAM]>;
// LDDW Rd+1:Rd, P+q
//
// Expands to:
// ldd Rd, P+q
// ldd Rd+1, P+q+1
- let Constraints = "@earlyclobber $dst" in
- def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst),
- (ins memri:$memri),
- "lddw\t$dst, $memri",
- [(set i16:$dst, (load addr:$memri))]>,
- Requires<[HasSRAM]>;
+ let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ
+ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND
+ : $dst),
+ (ins memri
+ : $memri),
+ "lddw\t$dst, $memri", [(set i16
+ : $dst, (load addr
+ : $memri))]>,
+ Requires<[HasSRAM]>;
// An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y
// register and without the @earlyclobber flag.
@@ -1270,7 +1407,8 @@ isReMaterializable = 1 in
// being able to handle the expansion of a COPY into an machine instruction
// that has an earlyclobber flag. This is because the register allocator will
// try expand a copy from a register slot into an earlyclobber instruction.
- // Instructions that are earlyclobber need to be in a dedicated earlyclobber slot.
+ // Instructions that are earlyclobber need to be in a dedicated earlyclobber
+ // slot.
//
// This pseudo instruction can be used pre-AVR pseudo expansion in order to
// get a frame index load without directly using earlyclobber instructions.
@@ -1279,30 +1417,44 @@ isReMaterializable = 1 in
//
// This instruction may be removed once PR13375 is fixed.
let mayLoad = 1,
- hasSideEffects = 0 in
- def LDDWRdYQ : Pseudo<(outs DREGS:$dst),
- (ins memri:$memri),
- "lddw\t$dst, $memri",
- []>,
- Requires<[HasSRAM]>;
+ hasSideEffects = 0 in def LDDWRdYQ : Pseudo<(outs DREGS
+ : $dst),
+ (ins memri
+ : $memri),
+ "lddw\t$dst, $memri", []>,
+ Requires<[HasSRAM]>;
}
-class AtomicLoad<PatFrag Op, RegisterClass DRC,
- RegisterClass PTRRC> :
- Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
- [(set DRC:$rd, (Op i16:$rr))]>;
-
-class AtomicStore<PatFrag Op, RegisterClass DRC,
- RegisterClass PTRRC> :
- Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
- [(Op i16:$rd, DRC:$rr)]>;
-
-let Constraints = "@earlyclobber $rd" in
-class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
- RegisterClass PTRRC> :
- Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
- "atomic_op",
- [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
+class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
+ : Pseudo<(outs DRC
+ : $rd),
+ (ins PTRRC
+ : $rr),
+ "atomic_op", [(set DRC
+ : $rd, (Op i16
+ : $rr))]>;
+
+class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
+ : Pseudo<(outs),
+ (ins PTRRC
+ : $rd, DRC
+ : $rr),
+ "atomic_op", [(Op i16
+ : $rd, DRC
+ : $rr)]>;
+
+let Constraints =
+ "@earlyclobber $rd" in class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
+ RegisterClass PTRRC>
+ : Pseudo<(outs DRC
+ : $rd),
+ (ins PTRRC
+ : $rr, DRC
+ : $operand),
+ "atomic_op", [(set DRC
+ : $rd, (Op i16
+ : $rr, DRC
+ : $operand))]>;
// FIXME: I think 16-bit atomic binary ops need to mark
// r0 as clobbered.
@@ -1318,34 +1470,36 @@ class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
// 16-bit operations use 16-bit load/store postincrement instructions,
// which require PTRDISPREGS.
-def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>;
-def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>;
+def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>;
+def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>;
-def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>;
+def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>;
def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>;
class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>;
class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>;
-def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>;
+def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>;
def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>;
-def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>;
+def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>;
def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>;
-def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>;
+def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>;
def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>;
-def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>;
-def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>;
-def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>;
+def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>;
+def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>;
+def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>;
def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>;
-def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
- [(atomic_fence timm, timm)]>;
+def AtomicFence
+ : Pseudo<(outs), (ins), "atomic_fence", [(atomic_fence timm, timm)]>;
// Indirect store from register to data space.
-def STSKRr : F32DM<0b1,
- (outs),
- (ins imm16:$k, GPR8:$rd),
- "sts\t$k, $rd",
- [(store i8:$rd, imm:$k)]>,
+def STSKRr : F32DM<0b1, (outs),
+ (ins imm16
+ : $k, GPR8
+ : $rd),
+ "sts\t$k, $rd", [(store i8
+ : $rd, imm
+ : $k)]>,
Requires<[HasSRAM]>;
// STSW K+1:K, Rr+1:Rr
@@ -1354,20 +1508,24 @@ def STSKRr : F32DM<0b1,
// sts Rr+1, (K+1:K) + 1
// sts Rr, (K+1:K)
def STSWKRr : Pseudo<(outs),
- (ins i16imm:$dst, DREGS:$src),
- "stsw\t$dst, $src",
- [(store i16:$src, imm:$dst)]>,
+ (ins i16imm
+ : $dst, DREGS
+ : $src),
+ "stsw\t$dst, $src", [(store i16
+ : $src, imm
+ : $dst)]>,
Requires<[HasSRAM]>;
// Indirect stores.
// ST P, Rr
// Stores the value of Rr into the location addressed by pointer P.
-def STPtrRr : FSTLD<1,
- 0b00,
- (outs),
- (ins LDSTPtrReg:$ptrreg, GPR8:$reg),
- "st\t$ptrreg, $reg",
- [(store GPR8:$reg, i16:$ptrreg)]>,
+def STPtrRr : FSTLD<1, 0b00, (outs),
+ (ins LDSTPtrReg
+ : $ptrreg, GPR8
+ : $reg),
+ "st\t$ptrreg, $reg", [(store GPR8
+ : $reg, i16
+ : $ptrreg)]>,
Requires<[HasSRAM]>;
// STW P, Rr+1:Rr
@@ -1377,25 +1535,32 @@ def STPtrRr : FSTLD<1,
// st P, Rr
// std P+1, Rr+1
def STWPtrRr : Pseudo<(outs),
- (ins PTRDISPREGS:$ptrreg, DREGS:$reg),
- "stw\t$ptrreg, $reg",
- [(store i16:$reg, i16:$ptrreg)]>,
+ (ins PTRDISPREGS
+ : $ptrreg, DREGS
+ : $reg),
+ "stw\t$ptrreg, $reg", [(store i16
+ : $reg, i16
+ : $ptrreg)]>,
Requires<[HasSRAM]>;
// Indirect stores (with postincrement or predecrement).
-let Constraints = "$ptrreg = $base_wb, at earlyclobber $base_wb" in
-{
+let Constraints = "$ptrreg = $base_wb, at earlyclobber $base_wb" in {
// ST P+, Rr
// Stores the value of Rr into the location addressed by pointer P.
// Post increments P.
- def STPtrPiRr : FSTLD<1,
- 0b01,
- (outs LDSTPtrReg:$base_wb),
- (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
- "st\t$ptrreg+, $reg",
- [(set i16:$base_wb,
- (post_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,
+ def STPtrPiRr : FSTLD<1, 0b01,
+ (outs LDSTPtrReg
+ : $base_wb),
+ (ins LDSTPtrReg
+ : $ptrreg, GPR8
+ : $reg, i8imm
+ : $offs),
+ "st\t$ptrreg+, $reg", [(set i16
+ : $base_wb, (post_store GPR8
+ : $reg, i16
+ : $ptrreg, imm
+ : $offs))]>,
Requires<[HasSRAM]>;
// STW P+, Rr+1:Rr
@@ -1405,23 +1570,34 @@ let Constraints = "$ptrreg = $base_wb, at earlyclobber $base_wb" in
// Expands to:
// st P+, Rr
// st P+, Rr+1
- def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb),
- (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs),
- "stw\t$ptrreg+, $trh",
- [(set PTRREGS:$base_wb,
- (post_store DREGS:$trh, PTRREGS:$ptrreg, imm:$offs))]>,
+ def STWPtrPiRr : Pseudo<(outs PTRREGS
+ : $base_wb),
+ (ins PTRREGS
+ : $ptrreg, DREGS
+ : $trh, i8imm
+ : $offs),
+ "stw\t$ptrreg+, $trh", [(set PTRREGS
+ : $base_wb, (post_store DREGS
+ : $trh, PTRREGS
+ : $ptrreg, imm
+ : $offs))]>,
Requires<[HasSRAM]>;
// ST -P, Rr
// Stores the value of Rr into the location addressed by pointer P.
// Pre decrements P.
- def STPtrPdRr : FSTLD<1,
- 0b10,
- (outs LDSTPtrReg:$base_wb),
- (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
- "st\t-$ptrreg, $reg",
- [(set i16:$base_wb,
- (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,
+ def STPtrPdRr : FSTLD<1, 0b10,
+ (outs LDSTPtrReg
+ : $base_wb),
+ (ins LDSTPtrReg
+ : $ptrreg, GPR8
+ : $reg, i8imm
+ : $offs),
+ "st\t-$ptrreg, $reg", [(set i16
+ : $base_wb, (pre_store GPR8
+ : $reg, i16
+ : $ptrreg, imm
+ : $offs))]>,
Requires<[HasSRAM]>;
// STW -P, Rr+1:Rr
@@ -1431,11 +1607,17 @@ let Constraints = "$ptrreg = $base_wb, at earlyclobber $base_wb" in
// Expands to:
// st -P, Rr+1
// st -P, Rr
- def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb),
- (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs),
- "stw\t-$ptrreg, $reg",
- [(set PTRREGS:$base_wb,
- (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>,
+ def STWPtrPdRr : Pseudo<(outs PTRREGS
+ : $base_wb),
+ (ins PTRREGS
+ : $ptrreg, DREGS
+ : $reg, i8imm
+ : $offs),
+ "stw\t-$ptrreg, $reg", [(set PTRREGS
+ : $base_wb, (pre_store i16
+ : $reg, i16
+ : $ptrreg, imm
+ : $offs))]>,
Requires<[HasSRAM]>;
}
@@ -1443,11 +1625,13 @@ let Constraints = "$ptrreg = $base_wb, at earlyclobber $base_wb" in
// STD P+q, Rr
// Stores the value of Rr into the location addressed by pointer P with a
// displacement of q. Does not modify P.
-def STDPtrQRr : FSTDLDD<1,
- (outs),
- (ins memri:$memri, GPR8:$reg),
- "std\t$memri, $reg",
- [(store i8:$reg, addr:$memri)]>,
+def STDPtrQRr : FSTDLDD<1, (outs),
+ (ins memri
+ : $memri, GPR8
+ : $reg),
+ "std\t$memri, $reg", [(store i8
+ : $reg, addr
+ : $memri)]>,
Requires<[HasSRAM]>;
// STDW P+q, Rr+1:Rr
@@ -1458,206 +1642,192 @@ def STDPtrQRr : FSTDLDD<1,
// std P+q, Rr
// std P+q+1, Rr+1
def STDWPtrQRr : Pseudo<(outs),
- (ins memri:$memri, DREGS:$src),
- "stdw\t$memri, $src",
- [(store i16:$src, addr:$memri)]>,
+ (ins memri
+ : $memri, DREGS
+ : $src),
+ "stdw\t$memri, $src", [(store i16
+ : $src, addr
+ : $memri)]>,
Requires<[HasSRAM]>;
-
// Load program memory operations.
-let canFoldAsLoad = 1,
-isReMaterializable = 1,
-mayLoad = 1,
-hasSideEffects = 0 in
-{
+let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,
+ hasSideEffects = 0 in {
let Defs = [R0],
- Uses = [R31R30] in
- def LPM : F16<0b1001010111001000,
- (outs),
- (ins),
- "lpm",
- []>,
- Requires<[HasLPM]>;
-
- def LPMRdZ : FLPMX<0,
- 0,
- (outs GPR8:$dst),
- (ins ZREG:$z),
- "lpm\t$dst, $z",
- []>,
+ Uses = [R31R30] in def LPM
+ : F16<0b1001010111001000, (outs), (ins), "lpm", []>,
+ Requires<[HasLPM]>;
+
+ def LPMRdZ : FLPMX<0, 0,
+ (outs GPR8
+ : $dst),
+ (ins ZREG
+ : $z),
+ "lpm\t$dst, $z", []>,
Requires<[HasLPMX]>;
// Load program memory, while postincrementing the Z register.
- let Defs = [R31R30] in
- {
- def LPMRdZPi : FLPMX<0,
- 1,
- (outs GPR8:$dst),
- (ins ZREG:$z),
- "lpm\t$dst, $z+",
- []>,
+ let Defs = [R31R30] in {
+ def LPMRdZPi : FLPMX<0, 1,
+ (outs GPR8
+ : $dst),
+ (ins ZREG
+ : $z),
+ "lpm\t$dst, $z+", []>,
Requires<[HasLPMX]>;
- def LPMWRdZ : Pseudo<(outs DREGS:$dst),
- (ins ZREG:$z),
- "lpmw\t$dst, $z",
- []>,
+ def LPMWRdZ : Pseudo<(outs DREGS
+ : $dst),
+ (ins ZREG
+ : $z),
+ "lpmw\t$dst, $z", []>,
Requires<[HasLPMX]>;
- def LPMWRdZPi : Pseudo<(outs DREGS:$dst),
- (ins ZREG:$z),
- "lpmw\t$dst, $z+",
- []>,
+ def LPMWRdZPi : Pseudo<(outs DREGS
+ : $dst),
+ (ins ZREG
+ : $z),
+ "lpmw\t$dst, $z+", []>,
Requires<[HasLPMX]>;
}
}
// Extended load program memory operations.
-let mayLoad = 1,
-hasSideEffects = 0 in
-{
+let mayLoad = 1, hasSideEffects = 0 in {
let Defs = [R0],
- Uses = [R31R30] in
- def ELPM : F16<0b1001010111011000,
- (outs),
- (ins),
- "elpm",
- []>,
- Requires<[HasELPM]>;
-
- def ELPMRdZ : FLPMX<1,
- 0,
- (outs GPR8:$dst),
- (ins ZREG:$z),
- "elpm\t$dst, $z",
- []>,
+ Uses = [R31R30] in def ELPM
+ : F16<0b1001010111011000, (outs), (ins), "elpm", []>,
+ Requires<[HasELPM]>;
+
+ def ELPMRdZ : FLPMX<1, 0,
+ (outs GPR8
+ : $dst),
+ (ins ZREG
+ : $z),
+ "elpm\t$dst, $z", []>,
Requires<[HasELPMX]>;
- let Defs = [R31R30] in
- def ELPMRdZPi : FLPMX<1,
- 1,
- (outs GPR8:$dst),
- (ins ZREG: $z),
- "elpm\t$dst, $z+",
- []>,
- Requires<[HasELPMX]>;
+ let Defs = [R31R30] in def ELPMRdZPi : FLPMX<1, 1,
+ (outs GPR8
+ : $dst),
+ (ins ZREG
+ : $z),
+ "elpm\t$dst, $z+", []>,
+ Requires<[HasELPMX]>;
}
// Store program memory operations.
-let Uses = [R1, R0] in
-{
- let Uses = [R31R30, R1, R0] in
- def SPM : F16<0b1001010111101000,
- (outs),
- (ins),
- "spm",
- []>,
- Requires<[HasSPM]>;
-
- let Defs = [R31R30] in
- def SPMZPi : F16<0b1001010111111000,
- (outs),
- (ins ZREG:$z),
- "spm $z+",
- []>,
- Requires<[HasSPMX]>;
+let Uses = [R1, R0] in {
+ let Uses = [R31R30, R1, R0] in def SPM
+ : F16<0b1001010111101000, (outs), (ins), "spm", []>,
+ Requires<[HasSPM]>;
+
+ let Defs = [R31R30] in def SPMZPi : F16<0b1001010111111000, (outs),
+ (ins ZREG
+ : $z),
+ "spm $z+", []>,
+ Requires<[HasSPMX]>;
}
// Read data from IO location operations.
-let canFoldAsLoad = 1,
-isReMaterializable = 1 in
-{
- def INRdA : FIORdA<(outs GPR8:$dst),
- (ins imm_port6:$src),
- "in\t$dst, $src",
- [(set i8:$dst, (load ioaddr8:$src))]>;
-
- def INWRdA : Pseudo<(outs DREGS:$dst),
- (ins imm_port6:$src),
- "inw\t$dst, $src",
- [(set i16:$dst, (load ioaddr16:$src))]>;
+let canFoldAsLoad = 1, isReMaterializable = 1 in {
+ def INRdA : FIORdA<(outs GPR8
+ : $dst),
+ (ins imm_port6
+ : $src),
+ "in\t$dst, $src", [(set i8
+ : $dst, (load ioaddr8
+ : $src))]>;
+
+ def INWRdA : Pseudo<(outs DREGS
+ : $dst),
+ (ins imm_port6
+ : $src),
+ "inw\t$dst, $src", [(set i16
+ : $dst, (load ioaddr16
+ : $src))]>;
}
// Write data to IO location operations.
def OUTARr : FIOARr<(outs),
- (ins imm_port6:$dst, GPR8:$src),
- "out\t$dst, $src",
- [(store i8:$src, ioaddr8:$dst)]>;
+ (ins imm_port6
+ : $dst, GPR8
+ : $src),
+ "out\t$dst, $src", [(store i8
+ : $src, ioaddr8
+ : $dst)]>;
def OUTWARr : Pseudo<(outs),
- (ins imm_port6:$dst, DREGS:$src),
- "outw\t$dst, $src",
- [(store i16:$src, ioaddr16:$dst)]>;
+ (ins imm_port6
+ : $dst, DREGS
+ : $src),
+ "outw\t$dst, $src", [(store i16
+ : $src, ioaddr16
+ : $dst)]>;
// Stack push/pop operations.
-let Defs = [SP],
-Uses = [SP],
-hasSideEffects = 0 in
-{
+let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
// Stack push operations.
- let mayStore = 1 in
- {
- def PUSHRr : FRd<0b1001,
- 0b0011111,
- (outs),
- (ins GPR8:$reg),
- "push\t$reg",
- []>,
+ let mayStore = 1 in {
+ def PUSHRr : FRd<0b1001, 0b0011111, (outs),
+ (ins GPR8
+ : $reg),
+ "push\t$reg", []>,
Requires<[HasSRAM]>;
def PUSHWRr : Pseudo<(outs),
- (ins DREGS:$reg),
- "pushw\t$reg",
- []>,
+ (ins DREGS
+ : $reg),
+ "pushw\t$reg", []>,
Requires<[HasSRAM]>;
}
// Stack pop operations.
- let mayLoad = 1 in
- {
- def POPRd : FRd<0b1001,
- 0b0001111,
- (outs GPR8:$reg),
- (ins),
- "pop\t$reg",
- []>,
+ let mayLoad = 1 in {
+ def POPRd : FRd<0b1001, 0b0001111,
+ (outs GPR8
+ : $reg),
+ (ins), "pop\t$reg", []>,
Requires<[HasSRAM]>;
- def POPWRd : Pseudo<(outs DREGS:$reg),
- (ins),
- "popw\t$reg",
- []>,
+ def POPWRd : Pseudo<(outs DREGS
+ : $reg),
+ (ins), "popw\t$reg", []>,
Requires<[HasSRAM]>;
}
}
// Read-Write-Modify (RMW) instructions.
def XCHZRd : FZRd<0b100,
- (outs GPR8:$rd),
- (ins ZREG:$z),
- "xch\t$z, $rd",
- []>,
+ (outs GPR8
+ : $rd),
+ (ins ZREG
+ : $z),
+ "xch\t$z, $rd", []>,
Requires<[SupportsRMW]>;
def LASZRd : FZRd<0b101,
- (outs GPR8:$rd),
- (ins ZREG:$z),
- "las\t$z, $rd",
- []>,
+ (outs GPR8
+ : $rd),
+ (ins ZREG
+ : $z),
+ "las\t$z, $rd", []>,
Requires<[SupportsRMW]>;
def LACZRd : FZRd<0b110,
- (outs GPR8:$rd),
- (ins ZREG:$z),
- "lac\t$z, $rd",
- []>,
+ (outs GPR8
+ : $rd),
+ (ins ZREG
+ : $z),
+ "lac\t$z, $rd", []>,
Requires<[SupportsRMW]>;
def LATZRd : FZRd<0b111,
- (outs GPR8:$rd),
- (ins ZREG:$z),
- "lat\t$z, $rd",
- []>,
+ (outs GPR8
+ : $rd),
+ (ins ZREG
+ : $z),
+ "lat\t$z, $rd", []>,
Requires<[SupportsRMW]>;
//===----------------------------------------------------------------------===//
@@ -1665,187 +1835,277 @@ def LATZRd : FZRd<0b111,
//===----------------------------------------------------------------------===//
// Bit shift/rotate operations.
-let Constraints = "$src = $rd",
-Defs = [SREG] in
-{
+let Constraints = "$src = $rd", Defs = [SREG] in {
// 8-bit LSL is an alias of ADD Rd, Rd
- def LSLWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
+ def LSLWRd : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
"lslw\t$rd",
- [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>;
-
- def LSLWNRd : Pseudo<(outs DLDREGS:$rd),
- (ins DREGS:$src, imm16:$bits),
- "lslwn\t$rd, $bits",
- [(set i16:$rd, (AVRlslwn i16:$src, imm:$bits)),
- (implicit SREG)]>;
-
- def LSLBNRd : Pseudo<(outs LD8:$rd),
- (ins GPR8:$src, imm_ldi8:$bits),
- "lslbn\t$rd, $bits",
- [(set i8:$rd, (AVRlslbn i8:$src, imm:$bits)),
- (implicit SREG)]>;
+ [(set i16
+ : $rd, (AVRlsl i16
+ : $src)),
+ (implicit SREG)]>;
- def LSRRd : FRd<0b1001,
- 0b0100110,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "lsr\t$rd",
- [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>;
+ def LSLWNRd : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DREGS
+ : $src, imm16
+ : $bits),
+ "lslwn\t$rd, $bits", [
+ (set i16
+ : $rd, (AVRlslwn i16
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def LSLBNRd : Pseudo<(outs LD8
+ : $rd),
+ (ins GPR8
+ : $src, imm_ldi8
+ : $bits),
+ "lslbn\t$rd, $bits", [
+ (set i8
+ : $rd, (AVRlslbn i8
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def LSRRd
+ : FRd<0b1001, 0b0100110,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "lsr\t$rd", [(set i8
+ : $rd, (AVRlsr i8
+ : $src)),
+ (implicit SREG)]>;
- def LSRWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
+ def LSRWRd : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
"lsrw\t$rd",
- [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
-
- def LSRWNRd : Pseudo<(outs DLDREGS:$rd),
- (ins DREGS:$src, imm16:$bits),
- "lsrwn\t$rd, $bits",
- [(set i16:$rd, (AVRlsrwn i16:$src, imm:$bits)),
- (implicit SREG)]>;
-
- def LSRBNRd : Pseudo<(outs LD8:$rd),
- (ins GPR8:$src, imm_ldi8:$bits),
- "lsrbn\t$rd, $bits",
- [(set i8:$rd, (AVRlsrbn i8:$src, imm:$bits)),
- (implicit SREG)]>;
-
- def ASRRd : FRd<0b1001,
- 0b0100101,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "asr\t$rd",
- [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>;
-
- def ASRWNRd : Pseudo<(outs DLDREGS:$rd),
- (ins DREGS:$src, imm16:$bits),
- "asrwn\t$rd, $bits",
- [(set i16:$rd, (AVRasrwn i16:$src, imm:$bits)),
- (implicit SREG)]>;
+ [(set i16
+ : $rd, (AVRlsr i16
+ : $src)),
+ (implicit SREG)]>;
- def ASRBNRd : Pseudo<(outs LD8:$rd),
- (ins GPR8:$src, imm_ldi8:$bits),
- "asrbn\t$rd, $bits",
- [(set i8:$rd, (AVRasrbn i8:$src, imm:$bits)),
- (implicit SREG)]>;
+ def LSRWNRd : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DREGS
+ : $src, imm16
+ : $bits),
+ "lsrwn\t$rd, $bits", [
+ (set i16
+ : $rd, (AVRlsrwn i16
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def LSRBNRd : Pseudo<(outs LD8
+ : $rd),
+ (ins GPR8
+ : $src, imm_ldi8
+ : $bits),
+ "lsrbn\t$rd, $bits", [
+ (set i8
+ : $rd, (AVRlsrbn i8
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def ASRRd
+ : FRd<0b1001, 0b0100101,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "asr\t$rd", [(set i8
+ : $rd, (AVRasr i8
+ : $src)),
+ (implicit SREG)]>;
- def ASRWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
+ def ASRWNRd : Pseudo<(outs DLDREGS
+ : $rd),
+ (ins DREGS
+ : $src, imm16
+ : $bits),
+ "asrwn\t$rd, $bits", [
+ (set i16
+ : $rd, (AVRasrwn i16
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def ASRBNRd : Pseudo<(outs LD8
+ : $rd),
+ (ins GPR8
+ : $src, imm_ldi8
+ : $bits),
+ "asrbn\t$rd, $bits", [
+ (set i8
+ : $rd, (AVRasrbn i8
+ : $src, imm
+ : $bits)),
+ (implicit SREG)
+ ]>;
+
+ def ASRWRd : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
"asrw\t$rd",
- [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>;
+ [(set i16
+ : $rd, (AVRasr i16
+ : $src)),
+ (implicit SREG)]>;
- def ROLBRd : Pseudo<(outs GPR8:$rd),
- (ins GPR8:$src),
+ def ROLBRd : Pseudo<(outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
"rolb\t$rd",
- [(set i8:$rd, (AVRrol i8:$src)), (implicit SREG)]>;
+ [(set i8
+ : $rd, (AVRrol i8
+ : $src)),
+ (implicit SREG)]>;
- def RORBRd : Pseudo<(outs GPR8:$rd),
- (ins GPR8:$src),
+ def RORBRd : Pseudo<(outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
"rorb\t$rd",
- [(set i8:$rd, (AVRror i8:$src)), (implicit SREG)]>;
+ [(set i8
+ : $rd, (AVRror i8
+ : $src)),
+ (implicit SREG)]>;
// Bit rotate operations.
- let Uses = [SREG] in
- {
-
- def ROLWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
- "rolw\t$rd",
- [(set i16:$rd, (AVRrol i16:$src)), (implicit SREG)]>;
-
- def RORRd : FRd<0b1001,
- 0b0100111,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "ror\t$rd",
- []>;
-
- def RORWRd : Pseudo<(outs DREGS:$rd),
- (ins DREGS:$src),
- "rorw\t$rd",
- [(set i16:$rd, (AVRror i16:$src)), (implicit SREG)]>;
+ let Uses = [SREG] in {
+
+ def ROLWRd
+ : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
+ "rolw\t$rd",
+ [(set i16
+ : $rd, (AVRrol i16
+ : $src)),
+ (implicit SREG)]>;
+
+ def RORRd : FRd<0b1001, 0b0100111,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "ror\t$rd", []>;
+
+ def RORWRd
+ : Pseudo<(outs DREGS
+ : $rd),
+ (ins DREGS
+ : $src),
+ "rorw\t$rd",
+ [(set i16
+ : $rd, (AVRror i16
+ : $src)),
+ (implicit SREG)]>;
}
}
// SWAP Rd
// Swaps the high and low nibbles in a register.
-let Constraints = "$src = $rd" in
-def SWAPRd : FRd<0b1001,
- 0b0100010,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "swap\t$rd",
- [(set i8:$rd, (AVRSwap i8:$src))]>;
+let Constraints =
+ "$src = $rd" in def SWAPRd : FRd<0b1001, 0b0100010,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src),
+ "swap\t$rd", [(set i8
+ : $rd, (AVRSwap i8
+ : $src))]>;
// IO register bit set/clear operations.
-//:TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi
+//: TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi
// instead of in+ori+out which requires one more instr.
-def SBIAb : FIOBIT<0b10,
- (outs),
- (ins imm_port5:$addr, i8imm:$bit),
- "sbi\t$addr, $bit",
- [(store (or (i8 (load lowioaddr8:$addr)), iobitpos8:$bit),
- lowioaddr8:$addr)]>;
-
-def CBIAb : FIOBIT<0b00,
- (outs),
- (ins imm_port5:$addr, i8imm:$bit),
- "cbi\t$addr, $bit",
- [(store (and (i8 (load lowioaddr8:$addr)), iobitposn8:$bit),
- lowioaddr8:$addr)]>;
+def SBIAb : FIOBIT<0b10, (outs),
+ (ins imm_port5
+ : $addr, i8imm
+ : $bit),
+ "sbi\t$addr, $bit", [(store(or(i8(load lowioaddr8
+ : $addr)),
+ iobitpos8
+ : $bit),
+ lowioaddr8
+ : $addr)]>;
+
+def CBIAb : FIOBIT<0b00, (outs),
+ (ins imm_port5
+ : $addr, i8imm
+ : $bit),
+ "cbi\t$addr, $bit", [(store(and(i8(load lowioaddr8
+ : $addr)),
+ iobitposn8
+ : $bit),
+ lowioaddr8
+ : $addr)]>;
// Status register bit load/store operations.
-let Defs = [SREG] in
-def BST : FRdB<0b01,
- (outs),
- (ins GPR8:$rd, i8imm:$b),
- "bst\t$rd, $b",
- []>;
+let Defs = [SREG] in def BST : FRdB<0b01, (outs),
+ (ins GPR8
+ : $rd, i8imm
+ : $b),
+ "bst\t$rd, $b", []>;
let Constraints = "$src = $rd",
-Uses = [SREG] in
-def BLD : FRdB<0b00,
- (outs GPR8:$rd),
- (ins GPR8:$src, i8imm:$b),
- "bld\t$rd, $b",
- []>;
+ Uses = [SREG] in def BLD : FRdB<0b00,
+ (outs GPR8
+ : $rd),
+ (ins GPR8
+ : $src, i8imm
+ : $b),
+ "bld\t$rd, $b", []>;
-def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8:$rd, imm_com8:$k), 0>;
+def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8 : $rd, imm_com8 : $k), 0>;
// CLR Rd
// Alias for EOR Rd, Rd
// -------------
// Clears all bits in a register.
-def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>;
+def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8 : $rd, GPR8 : $rd)>;
// LSL Rd
// Alias for ADD Rd, Rd
// --------------
// Logical shift left one bit.
-def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
+def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
-def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>;
+def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;
// SER Rd
// Alias for LDI Rd, 0xff
// ---------
// Sets all bits in a register.
-def : InstAlias<"ser\t$rd", (LDIRdK LD8:$rd, 0xff), 0>;
-
-let Defs = [SREG] in
-def BSETs : FS<0,
- (outs),
- (ins i8imm:$s),
- "bset\t$s",
- []>;
-
-let Defs = [SREG] in
-def BCLRs : FS<1,
- (outs),
- (ins i8imm:$s),
- "bclr\t$s",
- []>;
+def : InstAlias<"ser\t$rd", (LDIRdK LD8 : $rd, 0xff), 0>;
+
+let Defs = [SREG] in def BSETs : FS<0, (outs),
+ (ins i8imm
+ : $s),
+ "bset\t$s", []>;
+
+let Defs = [SREG] in def BCLRs : FS<1, (outs),
+ (ins i8imm
+ : $s),
+ "bclr\t$s", []>;
// Set/clear aliases for the carry (C) status flag (bit 0).
def : InstAlias<"sec", (BSETs 0)>;
@@ -1887,284 +2147,353 @@ def : InstAlias<"cli", (BCLRs 7)>;
// Breakpoint instruction
// ---------
// <|1001|0101|1001|1000>
-def BREAK : F16<0b1001010110011000,
- (outs),
- (ins),
- "break",
- []>,
+def BREAK : F16<0b1001010110011000, (outs), (ins), "break", []>,
Requires<[HasBREAK]>;
// NOP
// No-operation instruction
// ---------
// <|0000|0000|0000|0000>
-def NOP : F16<0b0000000000000000,
- (outs),
- (ins),
- "nop",
- []>;
+def NOP : F16<0b0000000000000000, (outs), (ins), "nop", []>;
// SLEEP
// Sleep instruction
// ---------
// <|1001|0101|1000|1000>
-def SLEEP : F16<0b1001010110001000,
- (outs),
- (ins),
- "sleep",
- []>;
+def SLEEP : F16<0b1001010110001000, (outs), (ins), "sleep", []>;
// WDR
// Watchdog reset
// ---------
// <|1001|0101|1010|1000>
-def WDR : F16<0b1001010110101000,
- (outs),
- (ins),
- "wdr",
- []>;
+def WDR : F16<0b1001010110101000, (outs), (ins), "wdr", []>;
//===----------------------------------------------------------------------===//
// Pseudo instructions for later expansion
//===----------------------------------------------------------------------===//
-//:TODO: Optimize this for wider types AND optimize the following code
+//: TODO: Optimize this for wider types AND optimize the following code
// compile int foo(char a, char b, char c, char d) {return d+b;}
// looks like a missed sext_inreg opportunity.
-def SEXT : ExtensionPseudo<
- (outs DREGS:$dst),
- (ins GPR8:$src),
- "sext\t$dst, $src",
- [(set i16:$dst, (sext i8:$src)), (implicit SREG)]
->;
-
-def ZEXT : ExtensionPseudo<
- (outs DREGS:$dst),
- (ins GPR8:$src),
- "zext\t$dst, $src",
- [(set i16:$dst, (zext i8:$src)), (implicit SREG)]
->;
+def SEXT
+ : ExtensionPseudo<(outs DREGS
+ : $dst),
+ (ins GPR8
+ : $src),
+ "sext\t$dst, $src",
+ [(set i16
+ : $dst, (sext i8
+ : $src)),
+ (implicit SREG)]>;
+
+def ZEXT
+ : ExtensionPseudo<(outs DREGS
+ : $dst),
+ (ins GPR8
+ : $src),
+ "zext\t$dst, $src",
+ [(set i16
+ : $dst, (zext i8
+ : $src)),
+ (implicit SREG)]>;
// This pseudo gets expanded into a movw+adiw thus it clobbers SREG.
let Defs = [SREG],
- hasSideEffects = 0 in
-def FRMIDX : Pseudo<(outs DLDREGS:$dst),
- (ins DLDREGS:$src, i16imm:$src2),
- "frmidx\t$dst, $src, $src2",
- []>;
+ hasSideEffects = 0 in def FRMIDX : Pseudo<(outs DLDREGS
+ : $dst),
+ (ins DLDREGS
+ : $src, i16imm
+ : $src2),
+ "frmidx\t$dst, $src, $src2", []>;
// This pseudo is either converted to a regular store or a push which clobbers
// SP.
-def STDSPQRr : StorePseudo<
- (outs),
- (ins memspi:$dst, GPR8:$src),
- "stdstk\t$dst, $src",
- [(store i8:$src, addr:$dst)]
->;
+def STDSPQRr : StorePseudo<(outs),
+ (ins memspi
+ : $dst, GPR8
+ : $src),
+ "stdstk\t$dst, $src", [(store i8
+ : $src, addr
+ : $dst)]>;
// This pseudo is either converted to a regular store or a push which clobbers
// SP.
-def STDWSPQRr : StorePseudo<
- (outs),
- (ins memspi:$dst, DREGS:$src),
- "stdwstk\t$dst, $src",
- [(store i16:$src, addr:$dst)]
->;
+def STDWSPQRr : StorePseudo<(outs),
+ (ins memspi
+ : $dst, DREGS
+ : $src),
+ "stdwstk\t$dst, $src", [(store i16
+ : $src, addr
+ : $dst)]>;
// SP read/write pseudos.
-let hasSideEffects = 0 in
-{
- let Uses = [SP] in
- def SPREAD : Pseudo<
- (outs DREGS:$dst),
- (ins GPRSP:$src),
- "spread\t$dst, $src",
- []
- >;
-
- let Defs = [SP] in
- def SPWRITE : Pseudo<
- (outs GPRSP:$dst),
- (ins DREGS:$src),
- "spwrite\t$dst, $src",
- []>;
+let hasSideEffects = 0 in {
+ let Uses = [SP] in def SPREAD : Pseudo<(outs DREGS
+ : $dst),
+ (ins GPRSP
+ : $src),
+ "spread\t$dst, $src", []>;
+
+ let Defs = [SP] in def SPWRITE : Pseudo<(outs GPRSP
+ : $dst),
+ (ins DREGS
+ : $src),
+ "spwrite\t$dst, $src", []>;
}
-def Select8 : SelectPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$src2, i8imm:$cc),
- "# Select8 PSEUDO",
- [(set i8:$dst, (AVRselectcc i8:$src, i8:$src2, imm:$cc))]
->;
-
-def Select16 : SelectPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, DREGS:$src2, i8imm:$cc),
- "# Select16 PSEUDO",
- [(set i16:$dst, (AVRselectcc i16:$src, i16:$src2, imm:$cc))]
->;
-
-def Lsl8 : ShiftPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$cnt),
- "# Lsl8 PSEUDO",
- [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))]
->;
-
-def Lsl16 : ShiftPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, GPR8:$cnt),
- "# Lsl16 PSEUDO",
- [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))]
->;
-
-def Lsr8 : ShiftPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$cnt),
- "# Lsr8 PSEUDO",
- [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))]
->;
-
-def Lsr16 : ShiftPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, GPR8:$cnt),
- "# Lsr16 PSEUDO",
- [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))]
->;
-
-def Rol8 : ShiftPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$cnt),
- "# Rol8 PSEUDO",
- [(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))]
->;
-
-def Rol16 : ShiftPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, GPR8:$cnt),
- "# Rol16 PSEUDO",
- [(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))]
->;
-
-def Ror8 : ShiftPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$cnt),
- "# Ror8 PSEUDO",
- [(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))]
->;
-
-def Ror16 : ShiftPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, GPR8:$cnt),
- "# Ror16 PSEUDO",
- [(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))]
->;
-
-def Asr8 : ShiftPseudo<
- (outs GPR8:$dst),
- (ins GPR8:$src, GPR8:$cnt),
- "# Asr8 PSEUDO",
- [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))]
->;
-
-def Asr16 : ShiftPseudo<
- (outs DREGS:$dst),
- (ins DREGS:$src, GPR8:$cnt),
- "# Asr16 PSEUDO",
- [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))]
->;
-
+def Select8 : SelectPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $src2, i8imm
+ : $cc),
+ "# Select8 PSEUDO", [(set i8
+ : $dst, (AVRselectcc i8
+ : $src, i8
+ : $src2, imm
+ : $cc))]>;
+
+def Select16 : SelectPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, DREGS
+ : $src2, i8imm
+ : $cc),
+ "# Select16 PSEUDO", [(set i16
+ : $dst, (AVRselectcc i16
+ : $src, i16
+ : $src2, imm
+ : $cc))]>;
+
+def Lsl8 : ShiftPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $cnt),
+ "# Lsl8 PSEUDO", [(set i8
+ : $dst, (AVRlslLoop i8
+ : $src, i8
+ : $cnt))]>;
+
+def Lsl16 : ShiftPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, GPR8
+ : $cnt),
+ "# Lsl16 PSEUDO", [(set i16
+ : $dst, (AVRlslLoop i16
+ : $src, i8
+ : $cnt))]>;
+
+def Lsr8 : ShiftPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $cnt),
+ "# Lsr8 PSEUDO", [(set i8
+ : $dst, (AVRlsrLoop i8
+ : $src, i8
+ : $cnt))]>;
+
+def Lsr16 : ShiftPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, GPR8
+ : $cnt),
+ "# Lsr16 PSEUDO", [(set i16
+ : $dst, (AVRlsrLoop i16
+ : $src, i8
+ : $cnt))]>;
+
+def Rol8 : ShiftPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $cnt),
+ "# Rol8 PSEUDO", [(set i8
+ : $dst, (AVRrolLoop i8
+ : $src, i8
+ : $cnt))]>;
+
+def Rol16 : ShiftPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, GPR8
+ : $cnt),
+ "# Rol16 PSEUDO", [(set i16
+ : $dst, (AVRrolLoop i16
+ : $src, i8
+ : $cnt))]>;
+
+def Ror8 : ShiftPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $cnt),
+ "# Ror8 PSEUDO", [(set i8
+ : $dst, (AVRrorLoop i8
+ : $src, i8
+ : $cnt))]>;
+
+def Ror16 : ShiftPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, GPR8
+ : $cnt),
+ "# Ror16 PSEUDO", [(set i16
+ : $dst, (AVRrorLoop i16
+ : $src, i8
+ : $cnt))]>;
+
+def Asr8 : ShiftPseudo<(outs GPR8
+ : $dst),
+ (ins GPR8
+ : $src, GPR8
+ : $cnt),
+ "# Asr8 PSEUDO", [(set i8
+ : $dst, (AVRasrLoop i8
+ : $src, i8
+ : $cnt))]>;
+
+def Asr16 : ShiftPseudo<(outs DREGS
+ : $dst),
+ (ins DREGS
+ : $src, GPR8
+ : $cnt),
+ "# Asr16 PSEUDO", [(set i16
+ : $dst, (AVRasrLoop i16
+ : $src, i8
+ : $cnt))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
-//:TODO: look in x86InstrCompiler.td for odd encoding trick related to
+//: TODO: look in x86InstrCompiler.td for odd encoding trick related to
// add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)
// the add instruction always writes the carry flag
-def : Pat<(addc i8:$src, i8:$src2),
- (ADDRdRr i8:$src, i8:$src2)>;
-def : Pat<(addc DREGS:$src, DREGS:$src2),
- (ADDWRdRr DREGS:$src, DREGS:$src2)>;
+def : Pat<(addc i8 : $src, i8 : $src2), (ADDRdRr i8 : $src, i8 : $src2)>;
+def : Pat<(addc DREGS
+ : $src, DREGS
+ : $src2),
+ (ADDWRdRr DREGS
+ : $src, DREGS
+ : $src2)>;
// all sub instruction variants always writes the carry flag
-def : Pat<(subc i8:$src, i8:$src2),
- (SUBRdRr i8:$src, i8:$src2)>;
-def : Pat<(subc i16:$src, i16:$src2),
- (SUBWRdRr i16:$src, i16:$src2)>;
-def : Pat<(subc i8:$src, imm:$src2),
- (SUBIRdK i8:$src, imm:$src2)>;
-def : Pat<(subc i16:$src, imm:$src2),
- (SUBIWRdK i16:$src, imm:$src2)>;
+def : Pat<(subc i8 : $src, i8 : $src2), (SUBRdRr i8 : $src, i8 : $src2)>;
+def : Pat<(subc i16 : $src, i16 : $src2), (SUBWRdRr i16 : $src, i16 : $src2)>;
+def : Pat<(subc i8 : $src, imm : $src2), (SUBIRdK i8 : $src, imm : $src2)>;
+def : Pat<(subc i16 : $src, imm : $src2), (SUBIWRdK i16 : $src, imm : $src2)>;
// These patterns convert add (x, -imm) to sub (x, imm) since we dont have
// any add with imm instructions. Also take care of the adiw/sbiw instructions.
-def : Pat<(add i16:$src1, imm0_63_neg:$src2),
- (SBIWRdK i16:$src1, (imm0_63_neg:$src2))>;
-def : Pat<(add i16:$src1, imm:$src2),
- (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
-def : Pat<(addc i16:$src1, imm:$src2),
- (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
-
-def : Pat<(add i8:$src1, imm:$src2),
- (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
-def : Pat<(addc i8:$src1, imm:$src2),
- (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
-def : Pat<(adde i8:$src1, imm:$src2),
- (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
+def : Pat<(add i16
+ : $src1, imm0_63_neg
+ : $src2),
+ (SBIWRdK i16
+ : $src1, (imm0_63_neg
+ : $src2))>;
+def : Pat<(add i16
+ : $src1, imm
+ : $src2),
+ (SUBIWRdK i16
+ : $src1, (imm16_neg_XFORM imm
+ : $src2))>;
+def : Pat<(addc i16
+ : $src1, imm
+ : $src2),
+ (SUBIWRdK i16
+ : $src1, (imm16_neg_XFORM imm
+ : $src2))>;
+
+def : Pat<(add i8
+ : $src1, imm
+ : $src2),
+ (SUBIRdK i8
+ : $src1, (imm8_neg_XFORM imm
+ : $src2))>;
+def : Pat<(addc i8
+ : $src1, imm
+ : $src2),
+ (SUBIRdK i8
+ : $src1, (imm8_neg_XFORM imm
+ : $src2))>;
+def : Pat<(adde i8
+ : $src1, imm
+ : $src2),
+ (SBCIRdK i8
+ : $src1, (imm8_neg_XFORM imm
+ : $src2))>;
// Calls.
-def : Pat<(AVRcall (i16 tglobaladdr:$dst)),
- (CALLk tglobaladdr:$dst)>;
-def : Pat<(AVRcall (i16 texternalsym:$dst)),
- (CALLk texternalsym:$dst)>;
+def : Pat<(AVRcall(i16 tglobaladdr : $dst)), (CALLk tglobaladdr : $dst)>;
+def : Pat<(AVRcall(i16 texternalsym : $dst)), (CALLk texternalsym : $dst)>;
// `anyext`
-def : Pat<(i16 (anyext i8:$src)),
- (INSERT_SUBREG (i16 (IMPLICIT_DEF)), i8:$src, sub_lo)>;
+def : Pat<(i16(anyext i8
+ : $src)),
+ (INSERT_SUBREG(i16(IMPLICIT_DEF)), i8
+ : $src, sub_lo)>;
// `trunc`
-def : Pat<(i8 (trunc i16:$src)),
- (EXTRACT_SUBREG i16:$src, sub_lo)>;
+def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>;
// sext_inreg
-def : Pat<(sext_inreg i16:$src, i8),
- (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>;
+def : Pat<(sext_inreg i16
+ : $src, i8),
+ (SEXT(i8(EXTRACT_SUBREG i16
+ : $src, sub_lo)))>;
// GlobalAddress
-def : Pat<(i16 (AVRWrapper tglobaladdr:$dst)),
- (LDIWRdK tglobaladdr:$dst)>;
-def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)),
- (SUBIWRdK i16:$src, tglobaladdr:$src2)>;
-def : Pat<(i8 (load (AVRWrapper tglobaladdr:$dst))),
- (LDSRdK tglobaladdr:$dst)>;
-def : Pat<(i16 (load (AVRWrapper tglobaladdr:$dst))),
- (LDSWRdK tglobaladdr:$dst)>;
-def : Pat<(store i8:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
- (STSKRr tglobaladdr:$dst, i8:$src)>;
-def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))),
- (STSWKRr tglobaladdr:$dst, i16:$src)>;
+def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>;
+def : Pat<(add i16
+ : $src, (AVRWrapper tglobaladdr
+ : $src2)),
+ (SUBIWRdK i16
+ : $src, tglobaladdr
+ : $src2)>;
+def : Pat<(i8(load(AVRWrapper tglobaladdr
+ : $dst))),
+ (LDSRdK tglobaladdr
+ : $dst)>;
+def : Pat<(i16(load(AVRWrapper tglobaladdr
+ : $dst))),
+ (LDSWRdK tglobaladdr
+ : $dst)>;
+def : Pat<(store i8
+ : $src, (i16(AVRWrapper tglobaladdr
+ : $dst))),
+ (STSKRr tglobaladdr
+ : $dst, i8
+ : $src)>;
+def : Pat<(store i16
+ : $src, (i16(AVRWrapper tglobaladdr
+ : $dst))),
+ (STSWKRr tglobaladdr
+ : $dst, i16
+ : $src)>;
// BlockAddress
-def : Pat<(i16 (AVRWrapper tblockaddress:$dst)),
- (LDIWRdK tblockaddress:$dst)>;
+def : Pat<(i16(AVRWrapper tblockaddress
+ : $dst)),
+ (LDIWRdK tblockaddress
+ : $dst)>;
-def : Pat<(i8 (trunc (AVRlsrwn DLDREGS:$src, (i16 8)))),
- (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
+def : Pat<(i8(trunc(AVRlsrwn DLDREGS
+ : $src, (i16 8)))),
+ (EXTRACT_SUBREG DREGS
+ : $src, sub_hi)>;
// :FIXME: DAGCombiner produces an shl node after legalization from these seq:
// BR_JT -> (mul x, 2) -> (shl x, 1)
-def : Pat<(shl i16:$src1, (i8 1)),
- (LSLWRd i16:$src1)>;
+def : Pat<(shl i16 : $src1, (i8 1)), (LSLWRd i16 : $src1)>;
// Lowering of 'tst' node to 'TST' instruction.
// TST is an alias of AND Rd, Rd.
-def : Pat<(AVRtst i8:$rd),
- (ANDRdRr GPR8:$rd, GPR8:$rd)>;
+def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
// Lowering of 'lsl' node to 'LSL' instruction.
// LSL is an alias of 'ADD Rd, Rd'
-def : Pat<(AVRlsl i8:$rd),
- (ADDRdRr GPR8:$rd, GPR8:$rd)>;
-
+def : Pat<(AVRlsl i8 : $rd), (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
diff --git a/llvm/lib/Target/AVR/AVRMCInstLower.cpp b/llvm/lib/Target/AVR/AVRMCInstLower.cpp
index 49a318762b638..2b8711656139d 100644
--- a/llvm/lib/Target/AVR/AVRMCInstLower.cpp
+++ b/llvm/lib/Target/AVR/AVRMCInstLower.cpp
@@ -29,7 +29,9 @@ MCOperand AVRMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
const MCExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
bool IsNegated = false;
- if (TF & AVRII::MO_NEG) { IsNegated = true; }
+ if (TF & AVRII::MO_NEG) {
+ IsNegated = true;
+ }
if (!MO.isJTI() && MO.getOffset()) {
Expr = MCBinaryExpr::createAdd(
@@ -59,7 +61,8 @@ MCOperand AVRMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
return MCOperand::createExpr(Expr);
}
-void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const {
+void AVRMCInstLower::lowerInstruction(const MachineInstr &MI,
+ MCInst &OutMI) const {
OutMI.setOpcode(MI.getOpcode());
for (MachineOperand const &MO : MI.operands()) {
@@ -108,4 +111,3 @@ void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) con
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/AVRMCInstLower.h b/llvm/lib/Target/AVR/AVRMCInstLower.h
index 5e0f42ac16a75..7ad6d472ad872 100644
--- a/llvm/lib/Target/AVR/AVRMCInstLower.h
+++ b/llvm/lib/Target/AVR/AVRMCInstLower.h
@@ -39,4 +39,3 @@ class AVRMCInstLower {
} // end namespace llvm
#endif // LLVM_AVR_MCINST_LOWER_H
-
diff --git a/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h b/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
index 5432fac122efb..8b1c247eb6a74 100644
--- a/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
+++ b/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
@@ -55,8 +55,10 @@ class AVRMachineFunctionInfo : public MachineFunctionInfo {
CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {
unsigned CallConv = MF.getFunction().getCallingConv();
- this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR || MF.getFunction().hasFnAttribute("interrupt");
- this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL || MF.getFunction().hasFnAttribute("signal");
+ this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR ||
+ MF.getFunction().hasFnAttribute("interrupt");
+ this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL ||
+ MF.getFunction().hasFnAttribute("signal");
}
bool getHasSpills() const { return HasSpills; }
@@ -69,7 +71,9 @@ class AVRMachineFunctionInfo : public MachineFunctionInfo {
void setHasStackArgs(bool B) { HasStackArgs = B; }
/// Checks if the function is some form of interrupt service routine.
- bool isInterruptOrSignalHandler() const { return isInterruptHandler() || isSignalHandler(); }
+ bool isInterruptOrSignalHandler() const {
+ return isInterruptHandler() || isSignalHandler();
+ }
bool isInterruptHandler() const { return IsInterruptHandler; }
bool isSignalHandler() const { return IsSignalHandler; }
@@ -81,6 +85,6 @@ class AVRMachineFunctionInfo : public MachineFunctionInfo {
void setVarArgsFrameIndex(int Idx) { VarArgsFrameIndex = Idx; }
};
-} // end llvm namespace
+} // namespace llvm
#endif // LLVM_AVR_MACHINE_FUNCTION_INFO_H
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
index 2a4905ce2461e..1886debaf492f 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
@@ -17,8 +17,8 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/IR/Function.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/IR/Function.h"
#include "AVR.h"
#include "AVRInstrInfo.h"
@@ -37,9 +37,8 @@ const uint16_t *
AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>();
- return AFI->isInterruptOrSignalHandler()
- ? CSR_Interrupts_SaveList
- : CSR_Normal_SaveList;
+ return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList
+ : CSR_Normal_SaveList;
}
const uint32_t *
@@ -47,9 +46,8 @@ AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
- return AFI->isInterruptOrSignalHandler()
- ? CSR_Interrupts_RegMask
- : CSR_Normal_RegMask;
+ return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_RegMask
+ : CSR_Normal_RegMask;
}
BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
@@ -207,7 +205,8 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// If the offset is too big we have to adjust and restore the frame pointer
// to materialize a valid load/store with displacement.
- //:TODO: consider using only one adiw/sbiw chain for more than one frame index
+ //: TODO: consider using only one adiw/sbiw chain for more than one frame
+ //: index
if (Offset > 62) {
unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
int AddOffset = Offset - 63 + 1;
@@ -276,18 +275,16 @@ void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg,
HiReg = getSubReg(Reg, AVR::sub_hi);
}
-bool AVRRegisterInfo::shouldCoalesce(MachineInstr *MI,
- const TargetRegisterClass *SrcRC,
- unsigned SubReg,
- const TargetRegisterClass *DstRC,
- unsigned DstSubReg,
- const TargetRegisterClass *NewRC,
- LiveIntervals &LIS) const {
- if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
+bool AVRRegisterInfo::shouldCoalesce(
+ MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
+ const TargetRegisterClass *DstRC, unsigned DstSubReg,
+ const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
+ if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
return false;
}
- return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
+ return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
+ NewRC, LIS);
}
} // end of namespace llvm
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.h b/llvm/lib/Target/AVR/AVRRegisterInfo.h
index 23439f2fe1957..fa27d9283209e 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.h
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.h
@@ -51,12 +51,9 @@ class AVRRegisterInfo : public AVRGenRegisterInfo {
/// \param Reg A 16-bit register to split.
void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
- bool shouldCoalesce(MachineInstr *MI,
- const TargetRegisterClass *SrcRC,
- unsigned SubReg,
- const TargetRegisterClass *DstRC,
- unsigned DstSubReg,
- const TargetRegisterClass *NewRC,
+ bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
+ unsigned SubReg, const TargetRegisterClass *DstRC,
+ unsigned DstSubReg, const TargetRegisterClass *NewRC,
LiveIntervals &LIS) const override;
};
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.td b/llvm/lib/Target/AVR/AVRRegisterInfo.td
index 1948fcbaf75ad..bb4e86ca0536f 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.td
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.td
@@ -11,12 +11,8 @@
//===----------------------------------------------------------------------===//
// 8-bit General purpose register definition.
-class AVRReg<bits<16> num,
- string name,
- list<Register> subregs = [],
- list<string> altNames = []>
- : RegisterWithSubRegs<name, subregs>
-{
+class AVRReg<bits<16> num, string name, list<Register> subregs = [],
+ list<string> altNames = []> : RegisterWithSubRegs<name, subregs> {
field bits<16> Num = num;
let HWEncoding = num;
@@ -26,31 +22,27 @@ class AVRReg<bits<16> num,
}
// Subregister indices.
-let Namespace = "AVR" in
-{
+let Namespace = "AVR" in {
def sub_lo : SubRegIndex<8>;
def sub_hi : SubRegIndex<8, 8>;
}
-let Namespace = "AVR" in {
- def ptr : RegAltNameIndex;
-}
-
+let Namespace = "AVR" in { def ptr : RegAltNameIndex; }
//===----------------------------------------------------------------------===//
// 8-bit general purpose registers
//===----------------------------------------------------------------------===//
-def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
-def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
-def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
-def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
-def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
-def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
-def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
-def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
-def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
-def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
+def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
+def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
+def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
+def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
+def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
+def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
+def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
+def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
+def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
+def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>;
def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
@@ -76,19 +68,17 @@ def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>;
def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>;
-let SubRegIndices = [sub_lo, sub_hi],
-CoveredBySubRegs = 1 in
-{
+let SubRegIndices = [sub_lo, sub_hi], CoveredBySubRegs = 1 in {
// 16 bit GPR pairs.
- def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>;
+ def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>;
// The pointer registers (X,Y,Z) are a special case because they
// are printed as a `high:low` pair when a DREG is expected,
// but printed using `X`, `Y`, `Z` when a pointer register is expected.
let RegAltNameIndices = [ptr] in {
- def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
- def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
- def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>;
+ def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
+ def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
+ def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>;
}
def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>;
@@ -98,11 +88,11 @@ CoveredBySubRegs = 1 in
def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
- def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
- def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
- def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>;
- def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>;
- def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>;
+ def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
+ def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
+ def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>;
+ def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>;
+ def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>;
// Pseudo registers for unaligned i16
def R26R25 : AVRReg<25, "r26:r25", [R25, R26]>, DwarfRegNum<[25]>;
@@ -113,7 +103,7 @@ CoveredBySubRegs = 1 in
def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
- def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>;
+ def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>;
}
//===----------------------------------------------------------------------===//
@@ -122,81 +112,71 @@ CoveredBySubRegs = 1 in
// Main 8-bit register class.
def GPR8 : RegisterClass<"AVR", [i8], 8,
- (
- // Return value and argument registers.
- add R24, R25, R18, R19, R20, R21, R22, R23,
- // Scratch registers.
- R30, R31, R26, R27,
- // Callee saved registers.
- R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
- R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
- )>;
+ (
+ // Return value and argument registers.
+ add R24, R25, R18, R19, R20, R21, R22, R23,
+ // Scratch registers.
+ R30, R31, R26, R27,
+ // Callee saved registers.
+ R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
+ R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
// Simple lower registers r0..r15
def GPR8lo : RegisterClass<"AVR", [i8], 8,
- (
- add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
- )>;
+ (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
+ R5, R4, R3, R2, R0, R1)>;
// 8-bit register class for instructions which take immediates.
def LD8 : RegisterClass<"AVR", [i8], 8,
- (
- // Return value and arguments.
- add R24, R25, R18, R19, R20, R21, R22, R23,
- // Scratch registers.
- R30, R31, R26, R27,
- // Callee saved registers.
- R28, R29, R17, R16
- )>;
+ (
+ // Return value and arguments.
+ add R24, R25, R18, R19, R20, R21, R22, R23,
+ // Scratch registers.
+ R30, R31, R26, R27,
+ // Callee saved registers.
+ R28, R29, R17, R16)>;
// Simple lower registers r16..r23
def LD8lo : RegisterClass<"AVR", [i8], 8,
- (
- add R23, R22, R21, R20, R19, R18, R17, R16
- )>;
+ (add R23, R22, R21, R20, R19, R18, R17, R16)>;
// Main 16-bit pair register class.
def DREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16, R15R14, R13R12, R11R10,
- R9R8, R7R6, R5R4, R3R2, R1R0,
- // Pseudo regs for unaligned 16-bits
- R26R25, R24R23, R22R21,
- R20R19, R18R17, R16R15,
- R14R13, R12R11, R10R9
- )>;
+ (
+ // Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
+ R7R6, R5R4, R3R2, R1R0,
+ // Pseudo regs for unaligned 16-bits
+ R26R25, R24R23, R22R21, R20R19, R18R17, R16R15,
+ R14R13, R12R11, R10R9)>;
// Lower 16-bit pair registers in R0..R15, only used in inline assembly.
-def DREGSlo : RegisterClass<"AVR", [i16], 8,
- (
- add R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2, R1R0
- )>;
+def DREGSlo
+ : RegisterClass<"AVR", [i16], 8,
+ (add R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2, R1R0)>;
// Lower 16-bit pair registers in r16..r23, only used in inline assembly.
def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R19R18, R21R20, R23R22,
- // Callee saved registers.
- R17R16
- )>;
+ (
+ // Return value and arguments.
+ add R19R18, R21R20, R23R22,
+ // Callee saved registers.
+ R17R16)>;
// 16-bit pair register class for movw
def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16, R15R14, R13R12, R11R10,
- R9R8, R7R6, R5R4, R3R2, R1R0
- )>;
+ (
+ // Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
+ R7R6, R5R4, R3R2, R1R0)>;
// The 16-bit DREGS register class, excluding the Z pointer register.
//
@@ -207,66 +187,59 @@ def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
// cannot use Z; it's simply a workaround a regalloc bug.
//
// More information can be found in PR39553.
-def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R27R26,
- // Callee saved registers.
- R17R16, R15R14, R13R12, R11R10,
- R9R8, R7R6, R5R4, R3R2, R1R0
- )>;
+def DREGS_WITHOUT_YZ_WORKAROUND
+ : RegisterClass<"AVR", [i16], 8,
+ (
+ // Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R27R26,
+ // Callee saved registers.
+ R17R16, R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2,
+ R1R0)>;
// 16-bit register class for immediate instructions.
def DLDREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16
- )>;
+ (
+ // Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16)>;
// 16-bit register class for the adiw/sbiw instructions.
def IWREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28
- )>;
+ (
+ // Return value and arguments.
+ add R25R24,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28)>;
// 16-bit register class for the ld and st instructions.
// AKA X,Y, and Z
def PTRREGS : RegisterClass<"AVR", [i16], 8,
- (
- add R27R26, // X
- R29R28, // Y
- R31R30 // Z
- ), ptr>;
+ (add R27R26, // X
+ R29R28, // Y
+ R31R30 // Z
+ ),
+ ptr>;
// 16-bit register class for the ldd and std instructions.
// AKA Y and Z.
-def PTRDISPREGS : RegisterClass<"AVR", [i16], 8,
- (
- add R31R30, R29R28
- ), ptr>;
+def PTRDISPREGS : RegisterClass<"AVR", [i16], 8, (add R31R30, R29R28), ptr>;
// We have a bunch of instructions with an explicit Z register argument. We
// model this using a register class containing only the Z register.
def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
// Register class used for the stack read pseudo instruction.
-def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>;
+def GPRSP : RegisterClass<"AVR", [i16], 8, (add SP)>;
// Status register.
def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>;
-def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>
-{
- let CopyCost = -1; // Don't allow copying of status registers
+def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> {
+ let CopyCost = -1; // Don't allow copying of status registers
}
-
diff --git a/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp b/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
index 7d2d19de7578c..76f29eb9f3697 100644
--- a/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
+++ b/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
@@ -84,8 +84,7 @@ bool AVRRelaxMem::runOnBasicBlock(Block &MBB) {
return Modified;
}
-template <>
-bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
+template <> bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
MachineOperand &Ptr = MI.getOperand(0);
@@ -96,24 +95,23 @@ bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
if (Imm > 63) {
// Push the previous state of the pointer register.
// This instruction must preserve the value.
- buildMI(MBB, MBBI, AVR::PUSHWRr)
- .addReg(Ptr.getReg());
+ buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(Ptr.getReg());
// Add the immediate to the pointer register.
buildMI(MBB, MBBI, AVR::SBCIWRdK)
- .addReg(Ptr.getReg(), RegState::Define)
- .addReg(Ptr.getReg())
- .addImm(-Imm);
+ .addReg(Ptr.getReg(), RegState::Define)
+ .addReg(Ptr.getReg())
+ .addImm(-Imm);
// Store the value in the source register to the address
// pointed to by the pointer register.
buildMI(MBB, MBBI, AVR::STWPtrRr)
- .addReg(Ptr.getReg())
- .addReg(Src.getReg(), getKillRegState(Src.isKill()));
+ .addReg(Ptr.getReg())
+ .addReg(Src.getReg(), getKillRegState(Src.isKill()));
// Pop the original state of the pointer register.
buildMI(MBB, MBBI, AVR::POPWRd)
- .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
+ .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
MI.removeFromParent();
}
@@ -125,21 +123,19 @@ bool AVRRelaxMem::runOnInstruction(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
int Opcode = MBBI->getOpcode();
-#define RELAX(Op) \
- case Op: \
+#define RELAX(Op) \
+ case Op: \
return relax<Op>(MBB, MI)
- switch (Opcode) {
- RELAX(AVR::STDWPtrQRr);
- }
+ switch (Opcode) { RELAX(AVR::STDWPtrQRr); }
#undef RELAX
return false;
}
} // end of anonymous namespace
-INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem",
- AVR_RELAX_MEM_OPS_NAME, false, false)
+INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem", AVR_RELAX_MEM_OPS_NAME, false,
+ false)
namespace llvm {
diff --git a/llvm/lib/Target/AVR/AVRSubtarget.h b/llvm/lib/Target/AVR/AVRSubtarget.h
index 7d49e43a83f52..90b9cd4da7c19 100644
--- a/llvm/lib/Target/AVR/AVRSubtarget.h
+++ b/llvm/lib/Target/AVR/AVRSubtarget.h
@@ -39,10 +39,18 @@ class AVRSubtarget : public AVRGenSubtargetInfo {
const AVRTargetMachine &TM);
const AVRInstrInfo *getInstrInfo() const override { return &InstrInfo; }
- const TargetFrameLowering *getFrameLowering() const override { return &FrameLowering; }
- const AVRTargetLowering *getTargetLowering() const override { return &TLInfo; }
- const AVRSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; }
- const AVRRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); }
+ const TargetFrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const AVRTargetLowering *getTargetLowering() const override {
+ return &TLInfo;
+ }
+ const AVRSelectionDAGInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
+ }
+ const AVRRegisterInfo *getRegisterInfo() const override {
+ return &InstrInfo.getRegisterInfo();
+ }
/// Parses a subtarget feature string, setting appropriate options.
/// \note Definition of function is auto generated by `tblgen`.
@@ -84,7 +92,6 @@ class AVRSubtarget : public AVRGenSubtargetInfo {
}
private:
-
/// The ELF e_flags architecture.
unsigned ELFArch;
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
index 5be4260ce0352..437034c532810 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -25,7 +25,8 @@
namespace llvm {
-static const char *AVRDataLayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
+static const char *AVRDataLayout =
+ "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
/// Processes a CPU name.
static StringRef getCPU(StringRef CPU) {
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h
index 8b8ae9e7ca8af..54669eda060c6 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.h
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.h
@@ -29,8 +29,7 @@ class AVRTargetMachine : public LLVMTargetMachine {
public:
AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
- Optional<Reloc::Model> RM,
- Optional<CodeModel::Model> CM,
+ Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
const AVRSubtarget *getSubtargetImpl() const;
diff --git a/llvm/lib/Target/AVR/AVRTargetObjectFile.cpp b/llvm/lib/Target/AVR/AVRTargetObjectFile.cpp
index 14206cdb82763..c7715ca1f51be 100644
--- a/llvm/lib/Target/AVR/AVRTargetObjectFile.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetObjectFile.cpp
@@ -24,10 +24,8 @@ void AVRTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {
Ctx.getELFSection(".progmem.data", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
}
-MCSection *
-AVRTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO,
- SectionKind Kind,
- const TargetMachine &TM) const {
+MCSection *AVRTargetObjectFile::SelectSectionForGlobal(
+ const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
// Global values in flash memory are placed in the progmem.data section
// unless they already have a user assigned section.
if (AVR::isProgramMemoryAddress(GO) && !GO->hasSection() && Kind.isReadOnly())
@@ -37,4 +35,3 @@ AVRTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO,
return Base::SelectSectionForGlobal(GO, Kind, TM);
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index 4f68cd8a53669..53aaa079c8e07 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -170,9 +170,11 @@ class AVROperand : public MCParsedAsmOperand {
}
bool isImmCom8() const {
- if (!isImm()) return false;
+ if (!isImm())
+ return false;
const auto *CE = dyn_cast<MCConstantExpr>(getImm());
- if (!CE) return false;
+ if (!CE)
+ return false;
int64_t Value = CE->getValue();
return isUInt<8>(Value);
}
@@ -322,11 +324,16 @@ bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
switch (MatchResult) {
- case Match_Success: return emit(Inst, Loc, Out);
- case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
- case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
- case Match_MnemonicFail: return Error(Loc, "invalid instruction");
- default: return true;
+ case Match_Success:
+ return emit(Inst, Loc, Out);
+ case Match_MissingFeature:
+ return missingFeature(Loc, ErrorInfo);
+ case Match_InvalidOperand:
+ return invalidOperand(Loc, Operands, ErrorInfo);
+ case Match_MnemonicFail:
+ return Error(Loc, "invalid instruction");
+ default:
+ return true;
}
}
@@ -440,8 +447,7 @@ bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
tokens[1].getKind() == AsmToken::Minus)) {
AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
- if (CurTok == AsmToken::Minus ||
- tokens[1].getKind() == AsmToken::Minus) {
+ if (CurTok == AsmToken::Minus || tokens[1].getKind() == AsmToken::Minus) {
isNegated = true;
} else {
assert(CurTok == AsmToken::Plus);
@@ -498,8 +504,8 @@ bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
assert(Parser.getTok().getKind() == AsmToken::RParen);
Parser.Lex(); // Eat closing parenthesis
- MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
- isNegated, getContext());
+ MCExpr const *Expression =
+ AVRMCExpr::create(ModifierKind, InnerExpression, isNegated, getContext());
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(AVROperand::CreateImm(Expression, S, E));
@@ -552,8 +558,7 @@ bool AVRAsmParser::parseOperand(OperandVector &Operands) {
return true;
}
-OperandMatchResultTy
-AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
+OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
SMLoc E, S;
@@ -620,7 +625,8 @@ bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
bool first = true;
while (getLexer().isNot(AsmToken::EndOfStatement)) {
- if (!first) eatComma();
+ if (!first)
+ eatComma();
first = false;
@@ -670,7 +676,7 @@ bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
Tokens[1].getKind() == AsmToken::Identifier) {
MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L,
- AVRMCExpr::VK_AVR_None);
+ AVRMCExpr::VK_AVR_None);
return false;
}
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 8e7251a74dfdf..64dfcf445ecc2 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -42,7 +42,7 @@ class AVRDisassembler : public MCDisassembler {
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const override;
};
-}
+} // namespace
static MCDisassembler *createAVRDisassembler(const Target &T,
const MCSubtargetInfo &STI,
@@ -50,7 +50,6 @@ static MCDisassembler *createAVRDisassembler(const Target &T,
return new AVRDisassembler(STI, Ctx);
}
-
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler() {
// Register the disassembler.
TargetRegistry::RegisterMCDisassembler(getTheAVRTarget(),
@@ -58,18 +57,16 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler() {
}
static const uint16_t GPRDecoderTable[] = {
- AVR::R0, AVR::R1, AVR::R2, AVR::R3,
- AVR::R4, AVR::R5, AVR::R6, AVR::R7,
- AVR::R8, AVR::R9, AVR::R10, AVR::R11,
- AVR::R12, AVR::R13, AVR::R14, AVR::R15,
- AVR::R16, AVR::R17, AVR::R18, AVR::R19,
- AVR::R20, AVR::R21, AVR::R22, AVR::R23,
- AVR::R24, AVR::R25, AVR::R26, AVR::R27,
- AVR::R28, AVR::R29, AVR::R30, AVR::R31,
+ AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,
+ AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
+ AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
+ AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
+ AVR::R28, AVR::R29, AVR::R30, AVR::R31,
};
static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
@@ -79,39 +76,41 @@ static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const void *Decoder) {
if (RegNo > 15)
return MCDisassembler::Fail;
- unsigned Register = GPRDecoderTable[RegNo+16];
+ unsigned Register = GPRDecoderTable[RegNo + 16];
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const void *Decoder) {
// Note: this function must be defined but does not seem to be called.
assert(false && "unimplemented: PTRREGS register class");
return MCDisassembler::Success;
}
-static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
-static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
-static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
-static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
@@ -119,40 +118,42 @@ static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder);
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
#include "AVRGenDisassemblerTables.inc"
-static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5);
Inst.addOperand(MCOperand::createImm(addr));
- if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
-static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5);
- if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(addr));
return MCDisassembler::Success;
}
-static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
unsigned addr = fieldFromInstruction(Insn, 3, 5);
unsigned b = fieldFromInstruction(Insn, 0, 3);
Inst.addOperand(MCOperand::createImm(addr));
@@ -168,16 +169,17 @@ static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
return MCDisassembler::Success;
}
-static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5);
- if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
-static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(AVR::R31R30));
@@ -188,9 +190,11 @@ static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
- if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
- if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
@@ -199,22 +203,26 @@ static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;
unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;
- if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
- if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
-static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn,
- uint64_t Address, const void *Decoder) {
+static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25
unsigned k = 0;
k |= fieldFromInstruction(Insn, 0, 4);
k |= fieldFromInstruction(Insn, 6, 2) << 4;
- if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
- if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(k));
return MCDisassembler::Success;
@@ -224,9 +232,11 @@ static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
- if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
- if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) == MCDisassembler::Fail)
+ if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
+ MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
@@ -253,7 +263,8 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
}
Size = 4;
- Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
+ Insn =
+ (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
return MCDisassembler::Success;
}
@@ -261,9 +272,12 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
static const uint8_t *getDecoderTable(uint64_t Size) {
switch (Size) {
- case 2: return DecoderTable16;
- case 4: return DecoderTable32;
- default: llvm_unreachable("instructions must be 16 or 32-bits");
+ case 2:
+ return DecoderTable16;
+ case 4:
+ return DecoderTable32;
+ default:
+ llvm_unreachable("instructions must be 16 or 32-bits");
}
}
@@ -279,11 +293,12 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
{
Result = readInstruction16(Bytes, Address, Size, Insn);
- if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;
+ if (Result == MCDisassembler::Fail)
+ return MCDisassembler::Fail;
// Try to auto-decode a 16-bit instruction.
- Result = decodeInstruction(getDecoderTable(Size), Instr,
- Insn, Address, this, STI);
+ Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address,
+ this, STI);
if (Result != MCDisassembler::Fail)
return Result;
@@ -293,10 +308,11 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
{
Result = readInstruction32(Bytes, Address, Size, Insn);
- if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;
+ if (Result == MCDisassembler::Fail)
+ return MCDisassembler::Fail;
- Result = decodeInstruction(getDecoderTable(Size), Instr, Insn,
- Address, this, STI);
+ Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address,
+ this, STI);
if (Result != MCDisassembler::Fail) {
return Result;
@@ -308,4 +324,3 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
const void *Decoder);
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
index 49840672bf9a0..692384e0a73e8 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
@@ -44,7 +44,7 @@ static void signed_width(unsigned Width, uint64_t Value,
int64_t Max = maxIntN(Width);
Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
- " to " + std::to_string(Max) + ")";
+ " to " + std::to_string(Max) + ")";
if (Ctx) {
Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
@@ -62,8 +62,8 @@ static void unsigned_width(unsigned Width, uint64_t Value,
int64_t Max = maxUIntN(Width);
- Diagnostic += " (expected an integer in the range 0 to " +
- std::to_string(Max) + ")";
+ Diagnostic +=
+ " (expected an integer in the range 0 to " + std::to_string(Max) + ")";
if (Ctx) {
Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
@@ -233,15 +233,14 @@ static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
ldi::fixup(Size, Fixup, Value, Ctx);
}
-} // end of ldi namespace
-} // end of adjust namespace
+} // namespace ldi
+} // namespace adjust
namespace llvm {
// Prepare value for the target space for it
void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
- const MCValue &Target,
- uint64_t &Value,
+ const MCValue &Target, uint64_t &Value,
MCContext *Ctx) const {
// The size of the fixup in bits.
uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
@@ -280,7 +279,8 @@ void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
break;
case AVR::fixup_hh8_ldi:
case AVR::fixup_hh8_ldi_pm:
- if (Kind == AVR::fixup_hh8_ldi_pm) adjust::pm(Value);
+ if (Kind == AVR::fixup_hh8_ldi_pm)
+ adjust::pm(Value);
adjust::ldi::hh8(Size, Fixup, Value, Ctx);
break;
@@ -290,21 +290,24 @@ void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
case AVR::fixup_lo8_ldi_neg:
case AVR::fixup_lo8_ldi_pm_neg:
- if (Kind == AVR::fixup_lo8_ldi_pm_neg) adjust::pm(Value);
+ if (Kind == AVR::fixup_lo8_ldi_pm_neg)
+ adjust::pm(Value);
adjust::ldi::neg(Value);
adjust::ldi::lo8(Size, Fixup, Value, Ctx);
break;
case AVR::fixup_hi8_ldi_neg:
case AVR::fixup_hi8_ldi_pm_neg:
- if (Kind == AVR::fixup_hi8_ldi_pm_neg) adjust::pm(Value);
+ if (Kind == AVR::fixup_hi8_ldi_pm_neg)
+ adjust::pm(Value);
adjust::ldi::neg(Value);
adjust::ldi::hi8(Size, Fixup, Value, Ctx);
break;
case AVR::fixup_hh8_ldi_neg:
case AVR::fixup_hh8_ldi_pm_neg:
- if (Kind == AVR::fixup_hh8_ldi_pm_neg) adjust::pm(Value);
+ if (Kind == AVR::fixup_hh8_ldi_pm_neg)
+ adjust::pm(Value);
adjust::ldi::neg(Value);
adjust::ldi::hh8(Size, Fixup, Value, Ctx);
@@ -468,8 +471,9 @@ bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
const MCFixup &Fixup,
const MCValue &Target) {
- switch ((unsigned) Fixup.getKind()) {
- default: return false;
+ switch ((unsigned)Fixup.getKind()) {
+ default:
+ return false;
// Fixups which should always be recorded as relocations.
case AVR::fixup_7_pcrel:
case AVR::fixup_13_pcrel:
@@ -485,4 +489,3 @@ MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI,
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
index 46dc914adf784..e6d37403c8391 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
@@ -67,4 +67,3 @@ class AVRAsmBackend : public MCAsmBackend {
} // end namespace llvm
#endif // LLVM_AVR_ASM_BACKEND_H
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
index bedf68db08ca7..b90e103794dae 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
@@ -27,21 +27,18 @@ class AVRELFObjectWriter : public MCELFObjectTargetWriter {
virtual ~AVRELFObjectWriter() {}
- unsigned getRelocType(MCContext &Ctx,
- const MCValue &Target,
- const MCFixup &Fixup,
- bool IsPCRel) const override;
+ unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+ const MCFixup &Fixup, bool IsPCRel) const override;
};
AVRELFObjectWriter::AVRELFObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(false, OSABI, ELF::EM_AVR, true) {}
-unsigned AVRELFObjectWriter::getRelocType(MCContext &Ctx,
- const MCValue &Target,
+unsigned AVRELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
- switch ((unsigned) Fixup.getKind()) {
+ switch ((unsigned)Fixup.getKind()) {
case FK_Data_1:
switch (Modifier) {
default:
@@ -158,4 +155,3 @@ std::unique_ptr<MCObjectTargetWriter> createAVRELFObjectWriter(uint8_t OSABI) {
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp
index 6d126ed622aa1..85933d6b9bb9d 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp
@@ -53,8 +53,7 @@ static unsigned getEFlagsForFeatureSet(const FeatureBitset &Features) {
return EFlags;
}
-AVRELFStreamer::AVRELFStreamer(MCStreamer &S,
- const MCSubtargetInfo &STI)
+AVRELFStreamer::AVRELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
: AVRTargetStreamer(S) {
MCAssembler &MCA = getStreamer().getAssembler();
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h
index a0dd1dc8ac3ec..1f7a926edb5cd 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h
@@ -141,7 +141,7 @@ namespace fixups {
template <typename T> inline void adjustBranchTarget(T &val) { val >>= 1; }
} // end of namespace fixups
-}
-} // end of namespace llvm::AVR
+} // namespace AVR
+} // namespace llvm
#endif // LLVM_AVR_FIXUP_KINDS_H
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 42fac5e2e000e..d68e73ce0bb15 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -172,7 +172,8 @@ void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
- assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand");
+ assert(MI->getOperand(OpNo).isReg() &&
+ "Expected a register for the first operand");
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
@@ -195,4 +196,3 @@ void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
index 8976ef28f3dca..11f55f6d253b6 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
@@ -56,4 +56,3 @@ class AVRInstPrinter : public MCInstPrinter {
} // end namespace llvm
#endif // LLVM_AVR_INST_PRINTER_H
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
index 50872d6d7a922..9754ff7f1146f 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
@@ -75,7 +75,7 @@ AVRMCCodeEmitter::loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
// check whether either of the registers are the X pointer register.
bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 ||
- MI.getOperand(1).getReg() == AVR::R27R26;
+ MI.getOperand(1).getReg() == AVR::R27R26;
bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
@@ -96,8 +96,8 @@ AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- MCFixupKind(Fixup), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup), MI.getLoc()));
return 0;
}
@@ -119,9 +119,12 @@ unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
assert(MO.isReg());
switch (MO.getReg()) {
- case AVR::R27R26: return 0x03; // X: 0b11
- case AVR::R29R28: return 0x02; // Y: 0b10
- case AVR::R31R30: return 0x00; // Z: 0b00
+ case AVR::R27R26:
+ return 0x03; // X: 0b11
+ case AVR::R29R28:
+ return 0x02; // Y: 0b10
+ case AVR::R31R30:
+ return 0x00; // Z: 0b00
default:
llvm_unreachable("invalid pointer register");
}
@@ -159,7 +162,7 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
} else if (OffsetOp.isExpr()) {
OffsetBits = 0;
Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
- MCFixupKind(AVR::fixup_6), MI.getLoc()));
+ MCFixupKind(AVR::fixup_6), MI.getLoc()));
} else {
llvm_unreachable("invalid value for offset");
}
@@ -193,7 +196,8 @@ unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
}
MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
- Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
return 0;
}
@@ -251,8 +255,10 @@ unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
- if (MO.isImm()) return static_cast<unsigned>(MO.getImm());
+ if (MO.isReg())
+ return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
+ if (MO.isImm())
+ return static_cast<unsigned>(MO.getImm());
if (MO.isDFPImm())
return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
index 2e24d885c1551..1bfa79f26b278 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
@@ -109,7 +109,6 @@ class AVRMCCodeEmitter : public MCCodeEmitter {
MCContext &Ctx;
};
-} // end namespace of llvm.
+} // namespace llvm
#endif // LLVM_AVR_CODE_EMITTER_H
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
index 0743344bc1edd..5f2a5a82e41d6 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
@@ -13,8 +13,8 @@
#include "MCTargetDesc/AVRMCELFStreamer.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSymbol.h"
#define DEBUG_TYPE "avrmcelfstreamer"
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
index a4f8787e56673..7e735ffa6cec1 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
@@ -19,16 +19,15 @@ namespace llvm {
namespace {
const struct ModifierEntry {
- const char * const Spelling;
+ const char *const Spelling;
AVRMCExpr::VariantKind VariantKind;
} ModifierNames[] = {
{"lo8", AVRMCExpr::VK_AVR_LO8}, {"hi8", AVRMCExpr::VK_AVR_HI8},
{"hh8", AVRMCExpr::VK_AVR_HH8}, // synonym with hlo8
{"hlo8", AVRMCExpr::VK_AVR_HH8}, {"hhi8", AVRMCExpr::VK_AVR_HHI8},
- {"pm", AVRMCExpr::VK_AVR_PM},
- {"pm_lo8", AVRMCExpr::VK_AVR_PM_LO8}, {"pm_hi8", AVRMCExpr::VK_AVR_PM_HI8},
- {"pm_hh8", AVRMCExpr::VK_AVR_PM_HH8},
+ {"pm", AVRMCExpr::VK_AVR_PM}, {"pm_lo8", AVRMCExpr::VK_AVR_PM_LO8},
+ {"pm_hi8", AVRMCExpr::VK_AVR_PM_HI8}, {"pm_hh8", AVRMCExpr::VK_AVR_PM_HH8},
{"lo8_gs", AVRMCExpr::VK_AVR_LO8_GS}, {"hi8_gs", AVRMCExpr::VK_AVR_HI8_GS},
{"gs", AVRMCExpr::VK_AVR_GS},
@@ -81,7 +80,8 @@ bool AVRMCExpr::evaluateAsRelocatableImpl(MCValue &Result,
if (Value.isAbsolute()) {
Result = MCValue::get(evaluateAsInt64(Value.getConstant()));
} else {
- if (!Layout) return false;
+ if (!Layout)
+ return false;
MCContext &Context = Layout->getAssembler().getContext();
const MCSymbolRefExpr *Sym = Value.getSymA();
@@ -219,4 +219,3 @@ AVRMCExpr::VariantKind AVRMCExpr::getKindByName(StringRef Name) {
}
} // end of namespace llvm
-
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
index e35385ebd90a4..68589763f29ae 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
@@ -34,7 +34,7 @@ class AVRMCExpr : public MCTargetExpr {
VK_AVR_LO8_GS, ///< Corresponds to `lo8(gs())`.
VK_AVR_HI8_GS, ///< Corresponds to `hi8(gs())`.
- VK_AVR_GS, ///< Corresponds to `gs()`.
+ VK_AVR_GS, ///< Corresponds to `gs()`.
};
public:
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
index 95f4465924ccf..3fcd825a5d054 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
@@ -10,17 +10,17 @@
//
//===----------------------------------------------------------------------===//
+#include "AVRMCTargetDesc.h"
#include "AVRELFStreamer.h"
#include "AVRInstPrinter.h"
#include "AVRMCAsmInfo.h"
#include "AVRMCELFStreamer.h"
-#include "AVRMCTargetDesc.h"
#include "AVRTargetStreamer.h"
#include "TargetInfo/AVRTargetInfo.h"
#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -108,7 +108,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTargetMC() {
createAVRMCInstPrinter);
// Register the MC Code Emitter
- TargetRegistry::RegisterMCCodeEmitter(getTheAVRTarget(), createAVRMCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(getTheAVRTarget(),
+ createAVRMCCodeEmitter);
// Register the obj streamer
TargetRegistry::RegisterELFStreamer(getTheAVRTarget(), createMCStreamer);
@@ -124,4 +125,3 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTargetMC() {
// Register the asm backend (as little endian).
TargetRegistry::RegisterMCAsmBackend(getTheAVRTarget(), createAVRAsmBackend);
}
-
diff --git a/llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp b/llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
index 69b509b33e88b..64a780496c1c7 100644
--- a/llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
+++ b/llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
@@ -13,10 +13,9 @@ Target &getTheAVRTarget() {
static Target TheAVRTarget;
return TheAVRTarget;
}
-}
+} // namespace llvm
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTargetInfo() {
llvm::RegisterTarget<llvm::Triple::avr> X(llvm::getTheAVRTarget(), "avr",
"Atmel AVR Microcontroller", "AVR");
}
-
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