[PATCH] D109129: [ARM] Fix operands of `Int_eh_sjlj_longjmp`
Tee KOBAYASHI via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 4 02:00:45 PDT 2021
xtkoba updated this revision to Diff 370715.
xtkoba added a comment.
Diff context extended
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109129/new/
https://reviews.llvm.org/D109129
Files:
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMRegisterInfo.td
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -254,6 +254,16 @@
let DiagnosticString = "operand must be a register in range [r0, r14]";
}
+// GPRs without potential FPs. Used by eh_sjlj_longjmp().
+def GPRnofp : RegisterClass<"ARM", [i32], 32, (sub GPR, R7, R11)> {
+ let AltOrders = [(add LR, GPRnofp), (trunc GPRnofp, 7),
+ (add (trunc GPRnofp, 7), R12, LR, (shl GPRnofp, 7))];
+ let AltOrderSelect = [{
+ return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
+ }];
+ let DiagnosticString = "operand must be a register in range [r0, r15]";
+}
+
// GPRs without the PC. Some ARM instructions do not allow the PC in
// certain operand slots, particularly as the destination. Primarily
// useful for disassembly.
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -5909,10 +5909,10 @@
// FIXME: Non-IOS version(s)
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
- Defs = [ R7, LR, SP ] in {
-def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
+ Defs = [ R7, R11, LR, SP ] in {
+def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPRnofp:$src, GPRnofp:$scratch),
NoItinerary,
- [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
+ [(ARMeh_sjlj_longjmp GPRnofp:$src, GPRnofp:$scratch)]>,
Requires<[IsARM]>;
}
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