[llvm] 2aea581 - [NFC] Added testcase for PR48641
Dávid Bolvanský via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 4 01:44:45 PDT 2021
Author: Dávid Bolvanský
Date: 2021-09-04T10:44:39+02:00
New Revision: 2aea581004d20dccd6aa8483704acec9a56e2345
URL: https://github.com/llvm/llvm-project/commit/2aea581004d20dccd6aa8483704acec9a56e2345
DIFF: https://github.com/llvm/llvm-project/commit/2aea581004d20dccd6aa8483704acec9a56e2345.diff
LOG: [NFC] Added testcase for PR48641
Added:
llvm/test/Transforms/SimplifyCFG/pr48641.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SimplifyCFG/pr48641.ll b/llvm/test/Transforms/SimplifyCFG/pr48641.ll
new file mode 100644
index 0000000000000..b3b6404ef14fa
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/pr48641.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+
+define i32 @foo_add(i8* %arg, i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: @foo_add(
+; CHECK-NEXT: common.ret:
+; CHECK-NEXT: [[I:%.*]] = sext i32 [[ARG1:%.*]] to i64
+; CHECK-NEXT: [[I3:%.*]] = getelementptr inbounds i8, i8* [[ARG:%.*]], i64 [[I]]
+; CHECK-NEXT: [[I4:%.*]] = load i8, i8* [[I3]], align 1
+; CHECK-NEXT: [[I5:%.*]] = zext i8 [[I4]] to i32
+; CHECK-NEXT: [[I6:%.*]] = add nsw i32 [[I5]], [[ARG2:%.*]]
+; CHECK-NEXT: [[I7:%.*]] = icmp sgt i32 [[I6]], 255
+; CHECK-NEXT: [[I9:%.*]] = icmp sgt i32 [[I6]], 0
+; CHECK-NEXT: [[I10:%.*]] = select i1 [[I9]], i32 [[I6]], i32 0
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[I7]], i32 255, i32 [[I10]]
+; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
+;
+ %i = sext i32 %arg1 to i64
+ %i3 = getelementptr inbounds i8, i8* %arg, i64 %i
+ %i4 = load i8, i8* %i3, align 1
+ %i5 = zext i8 %i4 to i32
+ %i6 = add nsw i32 %i5, %arg2
+ %i7 = icmp sgt i32 %i6, 255
+ br i1 %i7, label %bb11, label %bb8
+
+bb8:
+ %i9 = icmp sgt i32 %i6, 0
+ %i10 = select i1 %i9, i32 %i6, i32 0
+ ret i32 %i10
+
+bb11:
+ ret i32 255
+}
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