[PATCH] D109260: [RISCV] Add SiFive cores E and S series

[Alexander Pivovarov via Phabricator via llvm-commits]

apivovarov marked 4 inline comments as done.
apivovarov added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:279
+
+def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
+                                                 FeatureStdExtM,
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craig.topper wrote:
> Can we sort these by leading digit, then by letter? That will keep most of the SiFive7Models together.
Well, it is sorted by `core_type + number` in all other places in LLVM codebase (including error messages). GCC also sorts them as [[ https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def | E-S-U ]]. As well as [[ https://www.sifive.com/risc-v-core-ip | sifive.com ]]


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https://reviews.llvm.org/D109260