[llvm] 8f4042e - [InstCombine] add tests for icmp of rotate (PR51566); NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-09-03T14:51:35-04:00
New Revision: 8f4042ee4084d773a7d73b4b62400ad5945cb798

URL: https://github.com/llvm/llvm-project/commit/8f4042ee4084d773a7d73b4b62400ad5945cb798
DIFF: https://github.com/llvm/llvm-project/commit/8f4042ee4084d773a7d73b4b62400ad5945cb798.diff

LOG: [InstCombine] add tests for icmp of rotate (PR51566); NFC

Added: 
    llvm/test/Transforms/InstCombine/icmp-fsh.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/icmp-fsh.ll b/llvm/test/Transforms/InstCombine/icmp-fsh.ll
new file mode 100644
index 0000000000000..15b631b72ea4a
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/icmp-fsh.ll
@@ -0,0 +1,143 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare i8 @llvm.fshl.i8(i8, i8, i8)
+declare i8 @llvm.fshr.i8(i8, i8, i8)
+declare <2 x i5> @llvm.fshl.v2i5(<2 x i5>, <2 x i5>, <2 x i5>)
+declare void @use(i8)
+
+define i1 @rotl_eq_0(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotl_eq_0(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i8 [[ROT]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp eq i8 %rot, 0
+  ret i1 %r
+}
+
+define i1 @rotl_ne_0(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotl_ne_0(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    call void @use(i8 [[ROT]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i8 [[ROT]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
+  call void @use(i8 %rot)
+  %r = icmp ne i8 %rot, 0
+  ret i1 %r
+}
+
+define i1 @rotl_eq_n1(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotl_eq_n1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i8 [[ROT]], -1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp eq i8 %rot, -1
+  ret i1 %r
+}
+
+define <2 x i1> @rotl_ne_n1(<2 x i5> %x, <2 x i5> %y) {
+; CHECK-LABEL: @rotl_ne_n1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call <2 x i5> @llvm.fshl.v2i5(<2 x i5> [[X:%.*]], <2 x i5> [[X]], <2 x i5> [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne <2 x i5> [[ROT]], <i5 -1, i5 -1>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %rot = tail call <2 x i5> @llvm.fshl.v2i5(<2 x i5>%x, <2 x i5> %x, <2 x i5> %y)
+  %r = icmp ne <2 x i5> %rot, <i5 -1, i5 -1>
+  ret <2 x i1> %r
+}
+
+define <2 x i1> @rotl_ne_n1_undef(<2 x i5> %x, <2 x i5> %y) {
+; CHECK-LABEL: @rotl_ne_n1_undef(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call <2 x i5> @llvm.fshl.v2i5(<2 x i5> [[X:%.*]], <2 x i5> [[X]], <2 x i5> [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne <2 x i5> [[ROT]], <i5 -1, i5 undef>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %rot = tail call <2 x i5> @llvm.fshl.v2i5(<2 x i5>%x, <2 x i5> %x, <2 x i5> %y)
+  %r = icmp ne <2 x i5> %rot, <i5 -1, i5 undef>
+  ret <2 x i1> %r
+}
+
+define i1 @rotr_eq_0(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_eq_0(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    call void @use(i8 [[ROT]])
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i8 [[ROT]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  call void @use(i8 %rot)
+  %r = icmp eq i8 %rot, 0
+  ret i1 %r
+}
+
+define i1 @rotr_ne_0(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_ne_0(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i8 [[ROT]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp ne i8 %rot, 0
+  ret i1 %r
+}
+
+define i1 @rotr_eq_n1(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_eq_n1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i8 [[ROT]], -1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp eq i8 %rot, -1
+  ret i1 %r
+}
+
+define i1 @rotr_ne_n1(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_ne_n1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i8 [[ROT]], -1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp ne i8 %rot, -1
+  ret i1 %r
+}
+
+define i1 @rotr_ne_1(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_ne_1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i8 [[ROT]], 1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp ne i8 %rot, 1
+  ret i1 %r
+}
+
+define i1 @rotr_sgt_n1(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_sgt_n1(
+; CHECK-NEXT:    [[ROT:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[Y:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i8 [[ROT]], -1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %rot = tail call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
+  %r = icmp sgt i8 %rot, -1
+  ret i1 %r
+}
+
+define i1 @fshr_sgt_n1(i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @fshr_sgt_n1(
+; CHECK-NEXT:    [[FSH:%.*]] = tail call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[Y:%.*]], i8 [[Z:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i8 [[FSH]], -1
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %fsh = tail call i8 @llvm.fshr.i8(i8 %x, i8 %y, i8 %z)
+  %r = icmp eq i8 %fsh, -1
+  ret i1 %r
+}