[PATCH] D109240: [GlobalISel] Build_vector artifact combine into copy

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: foad, arsenm, aemerson, paquette.
Herald added subscribers: kerbowa, rovka, nhaehnle, jvesely.
Petar.Avramovic requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Series of patches with original intention to get optimal code for unusual vector sizes after D107650 <https://reviews.llvm.org/D107650> (use merge/unmerge for more elements vector instead of insert/extract) lands.


https://reviews.llvm.org/D109240

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/add.vNi16.ll.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-add.vNi16-build-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll