[llvm] 9e3f86e - [AMDGPU][MC][NFC][DOC] Updated description of registers

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2021-09-03T13:09:54+03:00
New Revision: 9e3f86e273d07786f5efa41494581e4971d8b0c0

URL: https://github.com/llvm/llvm-project/commit/9e3f86e273d07786f5efa41494581e4971d8b0c0
DIFF: https://github.com/llvm/llvm-project/commit/9e3f86e273d07786f5efa41494581e4971d8b0c0.diff

LOG: [AMDGPU][MC][NFC][DOC] Updated description of registers

Corrected list of available register tuples to reflect changes introduced by
commits https://reviews.llvm.org/D103672 and https://reviews.llvm.org/D103800

See bug https://bugs.llvm.org/show_bug.cgi?id=51388

Added: 
    

Modified: 
    llvm/docs/AMDGPU/gfx10_vaddr_4.rst
    llvm/docs/AMDGPUOperandSyntax.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst b/llvm/docs/AMDGPU/gfx10_vaddr_4.rst
index c7ac072fb1c9c..3e6d0c8a2db06 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_4.rst
@@ -17,6 +17,6 @@ This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_syn
 *Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
 
 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`

diff  --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index d41f429bccb33..acfd1b60ff3af 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -31,7 +31,7 @@ Vector registers. There are 256 32-bit vector registers.
 
 A sequence of *vector* registers may be used to operate with more than 32 bits of data.
 
-Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 *vector* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 *vector* registers.
 
     =================================================== ====================================================================
     Syntax                                              Description
@@ -61,7 +61,7 @@ Note: *N* and *K* must satisfy the following conditions:
 * *N* <= *K*.
 * 0 <= *N* <= 255.
 * 0 <= *K* <= 255.
-* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 8, 16 or 32.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.
 
 GFX90A has an additional alignment requirement: pairs of *vector* registers must be even-aligned
 (first register must be even).
@@ -114,7 +114,7 @@ Accumulator registers. There are 256 32-bit accumulator registers.
 
 A sequence of *accumulator* registers may be used to operate with more than 32 bits of data.
 
-Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 *accumulator* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 *accumulator* registers.
 
     =================================================== ========================================================= ====================================================================
     Syntax                                              An Alternative Syntax (SP3)                               Description
@@ -144,7 +144,7 @@ Note: *N* and *K* must satisfy the following conditions:
 * *N* <= *K*.
 * 0 <= *N* <= 255.
 * 0 <= *K* <= 255.
-* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 8, 16 or 32.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.
 
 GFX90A has an additional alignment requirement: pairs of *accumulator* registers must be even-aligned
 (first register must be even).
@@ -185,7 +185,7 @@ Scalar 32-bit registers. The number of available *scalar* registers depends on G
     ======= ============================
 
 A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
-Assembler currently supports sequences of 1, 2, 4, 8, 16 and 32 *scalar* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 *scalar* registers.
 
 Pairs of *scalar* registers must be even-aligned (first register must be even).
 Sequences of 4 and more *scalar* registers must be quad-aligned.
@@ -221,7 +221,7 @@ Note: *N* and *K* must satisfy the following conditions:
 * *N* <= *K*.
 * 0 <= *N* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
 * 0 <= *K* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
-* *K-N+1* must be equal to 1, 2, 4, 8, 16 or 32.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.
 
 Examples:
 
@@ -273,7 +273,7 @@ The number of available *ttmp* registers depends on GPU:
     ======= ===========================
 
 A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
-Assembler currently supports sequences of 1, 2, 4, 8 and 16 *ttmp* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8 and 16 *ttmp* registers.
 
 Pairs of *ttmp* registers must be even-aligned (first register must be even).
 Sequences of 4 and more *ttmp* registers must be quad-aligned.
@@ -307,7 +307,7 @@ Note: *N* and *K* must satisfy the following conditions:
 * *N* <= *K*.
 * 0 <= *N* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
 * 0 <= *K* < *TMAX*, where *TMAX* is the number of available *ttmp* registers.
-* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 7, 8 or 16.
 
 Examples: