[PATCH] D109148: [DAGCombiner][VP] Fold zero-length or false-masked VP ops

[Simon Moll via Phabricator via llvm-commits]

simoll added a comment.

This makes sense. +1 for also doing the corresponding IR optimization in InstSimplify.

I am not so sure about pro-active type narrowing (introducing `insert_subvector` nodes), at least not for all targets: we take VP nodes pretty much raw in the VE backend.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:22044
+    break;
+  case ISD::VP_ADD:
+  case ISD::VP_AND:
----------------
You could use the property macros in `include/llvm/IR/VPIntrinsics.def` for this intead.
Eg, define `ISD::isVPBinaryOp(ISD)` amd `ISD::isVPReductionOP(ISD)` and use them here.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:22064
+    return DAG.getUNDEF(N->getValueType(0));
+  case ISD::VP_STORE:
+    // VP_STORE/VP_SCATTER can be eliminated but replaced by their chains.
----------------
`cast<MemSDNode>` and handle all mem ops generically?

`MemSDNode::getChain()` gives you the chain.

`MemSDNode::readMem()` tells you whether we need an `UNDEF`.

This should automatically handle the upcoming `strided_load/store`.


Repository:
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  https://reviews.llvm.org/D109148/new/

https://reviews.llvm.org/D109148